Commit dd65b964 authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull ARM new SoC support from Arnd Bergmann:
 "This adds initial support for two SoC families that have been under
  review for a while. In both cases, the origonal idea was to have a
  minimally functional version, but we ended up leaving out the clk
  drivers that are still under review and will be merged through the
  corresponding subsystem tree.

  The Nuvoton NPCM8xx is a 64-bit Baseboard Management Controller and
  based on the 32-bit NPCM7xx family but is now getting added to
  arch/arm64 as well.

  Sunplus SP7021, also known as Plus1, is a general-purpose
  System-in-Package design based on the 32-bit Cortex-A7 SoC on the main
  chip, plus an I/O chip and memory in the same"

* tag 'arm-newsoc-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (25 commits)
  MAINTAINERS: rectify entry for ARM/NUVOTON NPCM ARCHITECTURE
  arm64: defconfig: Add Nuvoton NPCM family support
  arm64: dts: nuvoton: Add initial NPCM845 EVB device tree
  arm64: dts: nuvoton: Add initial NPCM8XX device tree
  arm64: npcm: Add support for Nuvoton NPCM8XX BMC SoC
  dt-bindings: arm: npcm: Add nuvoton,npcm845 GCR compatible string
  dt-bindings: arm: npcm: Add nuvoton,npcm845 compatible string
  dt-bindings: arm: npcm: Add maintainer
  reset: npcm: Add NPCM8XX support
  dt-bindings: reset: npcm: Add support for NPCM8XX
  reset: npcm: using syscon instead of device data
  ARM: dts: nuvoton: add reset syscon property
  dt-bindings: reset: npcm: add GCR syscon property
  dt-binding: clk: npcm845: Add binding for Nuvoton NPCM8XX Clock
  dt-bindings: watchdog: npcm: Add npcm845 compatible string
  dt-bindings: timer: npcm: Add npcm845 compatible string
  ARM: dts: Add Sunplus SP7021-Demo-V3 board device tree
  ARM: sp7021_defconfig: Add Sunplus SP7021 defconfig
  ARM: sunplus: Add initial support for Sunplus SP7021 SoC
  irqchip: Add Sunplus SP7021 interrupt controller driver
  ...
parents 3a829d26 bccd70a7
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+7 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ title: NPCM Platforms Device Tree Bindings

maintainers:
  - Jonathan Neuschäfer <j.neuschaefer@gmx.net>
  - Tomer Maimon <tmaimon77@gmail.com>

properties:
  $nodename:
@@ -26,4 +27,10 @@ properties:
              - nuvoton,npcm750-evb         # NPCM750 evaluation board
          - const: nuvoton,npcm750

      - description: NPCM845 based boards
        items:
          - enum:
              - nuvoton,npcm845-evb         # NPCM845 evaluation board
          - const: nuvoton,npcm845

additionalProperties: true
+2 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ title: Global Control Registers block in Nuvoton SoCs

maintainers:
  - Jonathan Neuschäfer <j.neuschaefer@gmx.net>
  - Tomer Maimon <tmaimon77@gmail.com>

description:
  The Global Control Registers (GCR) are a block of registers in Nuvoton SoCs
@@ -20,6 +21,7 @@ properties:
      - enum:
          - nuvoton,wpcm450-gcr
          - nuvoton,npcm750-gcr
          - nuvoton,npcm845-gcr
      - const: syscon
      - const: simple-mfd

+29 −0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) Sunplus Co., Ltd. 2021
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/sunplus,sp7021.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Sunplus SP7021 Boards

maintainers:
  - qinjian <qinjian@cqplus1.com>

description: |
  ARM platforms using Sunplus SP7021, an ARM Cortex A7 (4-cores) based SoC.
  Wiki: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview

properties:
  $nodename:
    const: '/'
  compatible:
    items:
      - enum:
          - sunplus,sp7021-achip
          - sunplus,sp7021-demo-v3
      - const: sunplus,sp7021

additionalProperties: true

...
+49 −0
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/nuvoton,npcm845-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Nuvoton NPCM8XX Clock Controller Binding

maintainers:
  - Tomer Maimon <tmaimon77@gmail.com>

description: |
  Nuvoton Arbel BMC NPCM8XX contains an integrated clock controller, which
  generates and supplies clocks to all modules within the BMC.

properties:
  compatible:
    enum:
      - nuvoton,npcm845-clk

  reg:
    maxItems: 1

  '#clock-cells':
    const: 1
    description:
      See include/dt-bindings/clock/nuvoton,npcm8xx-clock.h for the full
      list of NPCM8XX clock IDs.

required:
  - compatible
  - reg
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    ahb {
        #address-cells = <2>;
        #size-cells = <2>;

        clock-controller@f0801000 {
            compatible = "nuvoton,npcm845-clk";
            reg = <0x0 0xf0801000 0x0 0x1000>;
            #clock-cells = <1>;
        };
    };
...
+52 −0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) Sunplus Co., Ltd. 2021
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/sunplus,sp7021-clkc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Sunplus SP7021 SoC Clock Controller

maintainers:
  - Qin Jian <qinjian@cqplus1.com>

properties:
  compatible:
    const: sunplus,sp7021-clkc

  reg:
    maxItems: 3

  clocks:
    maxItems: 1

  "#clock-cells":
    const: 1

required:
  - compatible
  - reg
  - clocks
  - "#clock-cells"

additionalProperties: false

examples:
  - |
    extclk: osc0 {
      compatible = "fixed-clock";
      #clock-cells = <0>;
      clock-frequency = <27000000>;
      clock-output-names = "extclk";
    };

    clkc: clock-controller@9c000004 {
      compatible = "sunplus,sp7021-clkc";
      reg = <0x9c000004 0x28>,
            <0x9c000200 0x44>,
            <0x9c000268 0x08>;
      clocks = <&extclk>;
      #clock-cells = <1>;
    };

...
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