Commit dd8f2298 authored by Jouni Högander's avatar Jouni Högander Committed by Animesh Manna
Browse files

drm/i915/psr: Move psr specific dpcd init into own function 



This patch is preparing adding panel replay specific dpcd init.

Cc: Arun R Murthy <arun.r.murthy@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarArun R Murthy <arun.r.murthy@intel.com>
Signed-off-by: default avatarJouni Högander <jouni.hogander@intel.com>
Signed-off-by: default avatarAnimesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231108072303.3414118-3-animesh.manna@intel.com
parent 48d054c2

drivers/gpu/drm/i915/display/intel_psr.c

+23 −18
Original line number Diff line number Diff line
@@ -475,27 +475,22 @@ static void intel_dp_get_su_granularity(struct intel_dp *intel_dp) 
	intel_dp->psr.su_y_granularity = y;

}



void intel_psr_init_dpcd(struct intel_dp *intel_dp)

static void _psr_init_dpcd(struct intel_dp *intel_dp)

{

	struct drm_i915_private *dev_priv =

	struct drm_i915_private *i915 =

		to_i915(dp_to_dig_port(intel_dp)->base.base.dev);



	drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,

			 sizeof(intel_dp->psr_dpcd));



	if (!intel_dp->psr_dpcd[0])

		return;

	drm_dbg_kms(&dev_priv->drm, "eDP panel supports PSR version %x\n",

	drm_dbg_kms(&i915->drm, "eDP panel supports PSR version %x\n",

		    intel_dp->psr_dpcd[0]);



	if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) {

		drm_dbg_kms(&dev_priv->drm,

		drm_dbg_kms(&i915->drm,

			    "PSR support not currently available for this panel\n");

		return;

	}



	if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {

		drm_dbg_kms(&dev_priv->drm,

		drm_dbg_kms(&i915->drm,

			    "Panel lacks power state control, PSR cannot be enabled\n");

		return;

	}
@@ -504,8 +499,8 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp) 
	intel_dp->psr.sink_sync_latency =

		intel_dp_get_sink_sync_latency(intel_dp);



	if (DISPLAY_VER(dev_priv) >= 9 &&

	    (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {

	if (DISPLAY_VER(i915) >= 9 &&

	    intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED) {

		bool y_req = intel_dp->psr_dpcd[1] &

			     DP_PSR2_SU_Y_COORDINATE_REQUIRED;

		bool alpm = intel_dp_get_alpm_status(intel_dp);
@@ -522,8 +517,19 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp) 
		 * GTC first.

		 */

		intel_dp->psr.sink_psr2_support = y_req && alpm;

		drm_dbg_kms(&dev_priv->drm, "PSR2 %ssupported\n",

		drm_dbg_kms(&i915->drm, "PSR2 %ssupported\n",

			    intel_dp->psr.sink_psr2_support ? "" : "not ");

	}

}



void intel_psr_init_dpcd(struct intel_dp *intel_dp)

{

	drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,

			 sizeof(intel_dp->psr_dpcd));



	if (intel_dp->psr_dpcd[0])

		_psr_init_dpcd(intel_dp);

	/* TODO: Add PR case here */



	if (intel_dp->psr.sink_psr2_support) {

		intel_dp->psr.colorimetry_support =
@@ -531,7 +537,6 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp) 
		intel_dp_get_su_granularity(intel_dp);

	}

}

}



static void hsw_psr_setup_aux(struct intel_dp *intel_dp)

{