Commit de2ae887 authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Georgi Djakov
Browse files

interconnect: qcom: sdx65: Retire DEFINE_QBCM 



The struct definition macros are hard to read and compare, expand them.

Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: default avatarBjorn Andersson <quic_bjorande@quicinc.com>
Link: https://lore.kernel.org/r/20230811-topic-icc_retire_macrosd-v1-15-c03aaeffc769@linaro.org


Signed-off-by: default avatarGeorgi Djakov <djakov@kernel.org>
parent 37474b02

drivers/interconnect/qcom/sdx65.c

+165 −20
Original line number Diff line number Diff line
@@ -604,26 +604,171 @@ static struct qcom_icc_node xs_sys_tcu_cfg = { 
	.buswidth = 8,

};



DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);

DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);

DEFINE_QBCM(bcm_pn0, "PN0", true, &qhm_snoc_cfg, &qhs_aoss, &qhs_apss, &qhs_audio, &qhs_blsp1, &qhs_clk_ctl, &qhs_crypto0_cfg, &qhs_ddrss_cfg, &qhs_ecc_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mss_cfg, &qhs_pcie_parf, &qhs_pdm, &qhs_prng, &qhs_qdss_cfg, &qhs_qpic, &qhs_sdc1, &qhs_snoc_cfg, &qhs_spmi_fetcher, &qhs_spmi_vgi_coex, &qhs_tcsr, &qhs_tlmm, &qhs_usb3, &qhs_usb3_phy, &srvc_snoc);

DEFINE_QBCM(bcm_pn1, "PN1", false, &xm_sdc1);

DEFINE_QBCM(bcm_pn2, "PN2", false, &qhm_audio, &qhm_spmi_fetcher1);

DEFINE_QBCM(bcm_pn3, "PN3", false, &qhm_blsp1, &qhm_qpic);

DEFINE_QBCM(bcm_pn4, "PN4", false, &qxm_crypto);

DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);

DEFINE_QBCM(bcm_sh1, "SH1", false, &qns_memnoc_snoc);

DEFINE_QBCM(bcm_sh3, "SH3", false, &xm_apps_rdwr);

DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_snoc_memnoc);

DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);

DEFINE_QBCM(bcm_sn2, "SN2", false, &xs_qdss_stm);

DEFINE_QBCM(bcm_sn3, "SN3", false, &xs_sys_tcu_cfg);

DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_pcie);

DEFINE_QBCM(bcm_sn6, "SN6", false, &qhm_qdss_bam, &xm_qdss_etr);

DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre_noc, &xm_pcie, &xm_usb3, &qns_aggre_noc);

DEFINE_QBCM(bcm_sn8, "SN8", false, &qnm_memnoc);

DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_memnoc_pcie);

DEFINE_QBCM(bcm_sn10, "SN10", false, &qnm_ipa, &xm_ipa2pcie_slv);

static struct qcom_icc_bcm bcm_ce0 = {

	.name = "CE0",

	.keepalive = false,

	.num_nodes = 1,

	.nodes = { &qxm_crypto },

};



static struct qcom_icc_bcm bcm_mc0 = {

	.name = "MC0",

	.keepalive = true,

	.num_nodes = 1,

	.nodes = { &ebi },

};



static struct qcom_icc_bcm bcm_pn0 = {

	.name = "PN0",

	.keepalive = true,

	.num_nodes = 26,

	.nodes = { &qhm_snoc_cfg,

		   &qhs_aoss,

		   &qhs_apss,

		   &qhs_audio,

		   &qhs_blsp1,

		   &qhs_clk_ctl,

		   &qhs_crypto0_cfg,

		   &qhs_ddrss_cfg,

		   &qhs_ecc_cfg,

		   &qhs_imem_cfg,

		   &qhs_ipa,

		   &qhs_mss_cfg,

		   &qhs_pcie_parf,

		   &qhs_pdm,

		   &qhs_prng,

		   &qhs_qdss_cfg,

		   &qhs_qpic,

		   &qhs_sdc1,

		   &qhs_snoc_cfg,

		   &qhs_spmi_fetcher,

		   &qhs_spmi_vgi_coex,

		   &qhs_tcsr,

		   &qhs_tlmm,

		   &qhs_usb3,

		   &qhs_usb3_phy,

		   &srvc_snoc

	},

};



static struct qcom_icc_bcm bcm_pn1 = {

	.name = "PN1",

	.keepalive = false,

	.num_nodes = 1,

	.nodes = { &xm_sdc1 },

};



static struct qcom_icc_bcm bcm_pn2 = {

	.name = "PN2",

	.keepalive = false,

	.num_nodes = 2,

	.nodes = { &qhm_audio, &qhm_spmi_fetcher1 },

};



static struct qcom_icc_bcm bcm_pn3 = {

	.name = "PN3",

	.keepalive = false,

	.num_nodes = 2,

	.nodes = { &qhm_blsp1, &qhm_qpic },

};



static struct qcom_icc_bcm bcm_pn4 = {

	.name = "PN4",

	.keepalive = false,

	.num_nodes = 1,

	.nodes = { &qxm_crypto },

};



static struct qcom_icc_bcm bcm_sh0 = {

	.name = "SH0",

	.keepalive = true,

	.num_nodes = 1,

	.nodes = { &qns_llcc },

};



static struct qcom_icc_bcm bcm_sh1 = {

	.name = "SH1",

	.keepalive = false,

	.num_nodes = 1,

	.nodes = { &qns_memnoc_snoc },

};



static struct qcom_icc_bcm bcm_sh3 = {

	.name = "SH3",

	.keepalive = false,

	.num_nodes = 1,

	.nodes = { &xm_apps_rdwr },

};



static struct qcom_icc_bcm bcm_sn0 = {

	.name = "SN0",

	.keepalive = true,

	.num_nodes = 1,

	.nodes = { &qns_snoc_memnoc },

};



static struct qcom_icc_bcm bcm_sn1 = {

	.name = "SN1",

	.keepalive = false,

	.num_nodes = 1,

	.nodes = { &qxs_imem },

};



static struct qcom_icc_bcm bcm_sn2 = {

	.name = "SN2",

	.keepalive = false,

	.num_nodes = 1,

	.nodes = { &xs_qdss_stm },

};



static struct qcom_icc_bcm bcm_sn3 = {

	.name = "SN3",

	.keepalive = false,

	.num_nodes = 1,

	.nodes = { &xs_sys_tcu_cfg },

};



static struct qcom_icc_bcm bcm_sn5 = {

	.name = "SN5",

	.keepalive = false,

	.num_nodes = 1,

	.nodes = { &xs_pcie },

};



static struct qcom_icc_bcm bcm_sn6 = {

	.name = "SN6",

	.keepalive = false,

	.num_nodes = 2,

	.nodes = { &qhm_qdss_bam, &xm_qdss_etr },

};



static struct qcom_icc_bcm bcm_sn7 = {

	.name = "SN7",

	.keepalive = false,

	.num_nodes = 4,

	.nodes = { &qnm_aggre_noc, &xm_pcie, &xm_usb3, &qns_aggre_noc },

};



static struct qcom_icc_bcm bcm_sn8 = {

	.name = "SN8",

	.keepalive = false,

	.num_nodes = 1,

	.nodes = { &qnm_memnoc },

};



static struct qcom_icc_bcm bcm_sn9 = {

	.name = "SN9",

	.keepalive = false,

	.num_nodes = 1,

	.nodes = { &qnm_memnoc_pcie },

};



static struct qcom_icc_bcm bcm_sn10 = {

	.name = "SN10",

	.keepalive = false,

	.num_nodes = 2,

	.nodes = { &qnm_ipa, &xm_ipa2pcie_slv },

};



static struct qcom_icc_bcm * const mc_virt_bcms[] = {

	&bcm_mc0,