Commit deb8d0fe authored by Jouni Högander's avatar Jouni Högander
Browse files

drm/i915/psr: Read all Panel Replay capability registers from DPCD 



There are several Panel Replay capability register in DPCD. Read them
all for later use.

v2:
  - avoid using hardcoded indices
  - read all Panel Replay capability registers

Signed-off-by: default avatarJouni Högander <jouni.hogander@intel.com>
Reviewed-by: default avatarAnkit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://lore.kernel.org/r/20250526120512.1702815-4-jouni.hogander@intel.com
parent 3e61b092

drivers/gpu/drm/i915/display/intel_display_types.h

+3 −1
Original line number Diff line number Diff line
@@ -1669,7 +1669,9 @@ struct intel_dp { 
	bool use_max_params;

	u8 dpcd[DP_RECEIVER_CAP_SIZE];

	u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];

	u8 pr_dpcd;

	u8 pr_dpcd[DP_PANEL_REPLAY_CAP_SIZE];

#define INTEL_PR_DPCD_INDEX(pr_dpcd_register)	((pr_dpcd_register) - DP_PANEL_REPLAY_CAP_SUPPORT)



	u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];

	u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];

	u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE];

drivers/gpu/drm/i915/display/intel_psr.c

+13 −7
Original line number Diff line number Diff line
@@ -608,7 +608,8 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp) 
			return;

		}



		if (!(intel_dp->pr_dpcd & DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)) {

		if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &

		      DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)) {

			drm_dbg_kms(display->drm,

				    "Panel doesn't support early transport, eDP Panel Replay not possible\n");

			return;
@@ -617,7 +618,8 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp) 


	intel_dp->psr.sink_panel_replay_support = true;



	if (intel_dp->pr_dpcd & DP_PANEL_REPLAY_SU_SUPPORT)

	if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &

	    DP_PANEL_REPLAY_SU_SUPPORT)

		intel_dp->psr.sink_panel_replay_su_support = true;



	drm_dbg_kms(display->drm,
@@ -676,10 +678,12 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp) 
{

	drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,

			 sizeof(intel_dp->psr_dpcd));

	drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP_SUPPORT,

			  &intel_dp->pr_dpcd);



	if (intel_dp->pr_dpcd & DP_PANEL_REPLAY_SUPPORT)

	drm_dp_dpcd_read(&intel_dp->aux, DP_PANEL_REPLAY_CAP_SUPPORT,

			 &intel_dp->pr_dpcd, sizeof(intel_dp->pr_dpcd));



	if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &

	    DP_PANEL_REPLAY_SUPPORT)

		_panel_replay_init_dpcd(intel_dp);



	if (intel_dp->psr_dpcd[0])
@@ -736,7 +740,8 @@ static bool psr2_su_region_et_valid(struct intel_dp *intel_dp, bool panel_replay 
		return false;



	return panel_replay ?

		intel_dp->pr_dpcd & DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT :

		intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &

		DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT :

		intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED &&

		psr2_su_region_et_global_enabled(intel_dp);

}
@@ -3916,7 +3921,8 @@ static void intel_psr_sink_capability(struct intel_dp *intel_dp, 
	seq_printf(m, ", Panel Replay = %s", str_yes_no(psr->sink_panel_replay_support));

	seq_printf(m, ", Panel Replay Selective Update = %s",

		   str_yes_no(psr->sink_panel_replay_su_support));

	if (intel_dp->pr_dpcd & DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)

	if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &

	    DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)

		seq_printf(m, " (Early Transport)");

	seq_printf(m, "\n");

}