Commit decc3684 authored by Besar Wicaksono's avatar Besar Wicaksono Committed by Will Deacon
Browse files

perf/arm_cspmu: nvidia: Add pmevfiltr2 support 



Support NVIDIA PMU that utilizes the optional event filter2 register.

Reviewed-by: default avatarIlkka Koskinen <ilkka@os.amperecomputing.com>
Signed-off-by: default avatarBesar Wicaksono <bwicaksono@nvidia.com>
Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 82dfd72b

drivers/perf/arm_cspmu/nvidia_cspmu.c

+133 −43
Original line number Diff line number Diff line
@@ -40,10 +40,21 @@ 


struct nv_cspmu_ctx {

	const char *name;

	u32 filter_mask;

	u32 filter_default_val;



	struct attribute **event_attr;

	struct attribute **format_attr;



	u32 filter_mask;

	u32 filter_default_val;

	u32 filter2_mask;

	u32 filter2_default_val;



	u32 (*get_filter)(const struct perf_event *event);

	u32 (*get_filter2)(const struct perf_event *event);



	void *data;



	int (*init_data)(struct arm_cspmu *cspmu);

};



static struct attribute *scf_pmu_event_attrs[] = {
@@ -144,6 +155,7 @@ static struct attribute *cnvlink_pmu_format_attrs[] = { 
static struct attribute *generic_pmu_format_attrs[] = {

	ARM_CSPMU_FORMAT_EVENT_ATTR,

	ARM_CSPMU_FORMAT_FILTER_ATTR,

	ARM_CSPMU_FORMAT_FILTER2_ATTR,

	NULL,

};
@@ -184,13 +196,36 @@ static u32 nv_cspmu_event_filter(const struct perf_event *event) 
	return filter_val;

}



static u32 nv_cspmu_event_filter2(const struct perf_event *event)

{

	const struct nv_cspmu_ctx *ctx =

		to_nv_cspmu_ctx(to_arm_cspmu(event->pmu));



	const u32 filter_val = event->attr.config2 & ctx->filter2_mask;



	if (filter_val == 0)

		return ctx->filter2_default_val;



	return filter_val;

}



static void nv_cspmu_set_ev_filter(struct arm_cspmu *cspmu,

				   const struct perf_event *event)

{

	u32 filter = nv_cspmu_event_filter(event);

	u32 offset = PMEVFILTR + (4 * event->hw.idx);

	u32 filter, offset;

	const struct nv_cspmu_ctx *ctx =

		to_nv_cspmu_ctx(to_arm_cspmu(event->pmu));

	offset = 4 * event->hw.idx;



	writel(filter, cspmu->base0 + offset);

	if (ctx->get_filter) {

		filter = ctx->get_filter(event);

		writel(filter, cspmu->base0 + PMEVFILTR + offset);

	}



	if (ctx->get_filter2) {

		filter = ctx->get_filter2(event);

		writel(filter, cspmu->base0 + PMEVFILT2R + offset);

	}

}



static void nv_cspmu_set_cc_filter(struct arm_cspmu *cspmu,
@@ -210,74 +245,120 @@ enum nv_cspmu_name_fmt { 
struct nv_cspmu_match {

	u32 prodid;

	u32 prodid_mask;

	u64 filter_mask;

	u32 filter_default_val;

	const char *name_pattern;

	enum nv_cspmu_name_fmt name_fmt;

	struct attribute **event_attr;

	struct attribute **format_attr;

	struct nv_cspmu_ctx template_ctx;

	struct arm_cspmu_impl_ops ops;

};



static const struct nv_cspmu_match nv_cspmu_match[] = {

	{

	  .prodid = 0x10300000,

	  .prodid_mask = NV_PRODID_MASK,

	  .filter_mask = NV_PCIE_FILTER_ID_MASK,

	  .filter_default_val = NV_PCIE_FILTER_ID_MASK,

	  .name_pattern = "nvidia_pcie_pmu_%u",

	  .name_fmt = NAME_FMT_SOCKET,

	  .template_ctx = {

		.event_attr = mcf_pmu_event_attrs,

	  .format_attr = pcie_pmu_format_attrs

		.format_attr = pcie_pmu_format_attrs,

		.filter_mask = NV_PCIE_FILTER_ID_MASK,

		.filter_default_val = NV_PCIE_FILTER_ID_MASK,

		.filter2_mask = 0x0,

		.filter2_default_val = 0x0,

		.get_filter = nv_cspmu_event_filter,

		.get_filter2 = NULL,

		.data = NULL,

		.init_data = NULL

	  },

	},

	{

	  .prodid = 0x10400000,

	  .prodid_mask = NV_PRODID_MASK,

	  .filter_mask = NV_NVL_C2C_FILTER_ID_MASK,

	  .filter_default_val = NV_NVL_C2C_FILTER_ID_MASK,

	  .name_pattern = "nvidia_nvlink_c2c1_pmu_%u",

	  .name_fmt = NAME_FMT_SOCKET,

	  .template_ctx = {

		.event_attr = mcf_pmu_event_attrs,

	  .format_attr = nvlink_c2c_pmu_format_attrs

		.format_attr = nvlink_c2c_pmu_format_attrs,

		.filter_mask = NV_NVL_C2C_FILTER_ID_MASK,

		.filter_default_val = NV_NVL_C2C_FILTER_ID_MASK,

		.filter2_mask = 0x0,

		.filter2_default_val = 0x0,

		.get_filter = nv_cspmu_event_filter,

		.get_filter2 = NULL,

		.data = NULL,

		.init_data = NULL

	  },

	},

	{

	  .prodid = 0x10500000,

	  .prodid_mask = NV_PRODID_MASK,

	  .filter_mask = NV_NVL_C2C_FILTER_ID_MASK,

	  .filter_default_val = NV_NVL_C2C_FILTER_ID_MASK,

	  .name_pattern = "nvidia_nvlink_c2c0_pmu_%u",

	  .name_fmt = NAME_FMT_SOCKET,

	  .template_ctx = {

		.event_attr = mcf_pmu_event_attrs,

	  .format_attr = nvlink_c2c_pmu_format_attrs

		.format_attr = nvlink_c2c_pmu_format_attrs,

		.filter_mask = NV_NVL_C2C_FILTER_ID_MASK,

		.filter_default_val = NV_NVL_C2C_FILTER_ID_MASK,

		.filter2_mask = 0x0,

		.filter2_default_val = 0x0,

		.get_filter = nv_cspmu_event_filter,

		.get_filter2 = NULL,

		.data = NULL,

		.init_data = NULL

	  },

	},

	{

	  .prodid = 0x10600000,

	  .prodid_mask = NV_PRODID_MASK,

	  .filter_mask = NV_CNVL_FILTER_ID_MASK,

	  .filter_default_val = NV_CNVL_FILTER_ID_MASK,

	  .name_pattern = "nvidia_cnvlink_pmu_%u",

	  .name_fmt = NAME_FMT_SOCKET,

	  .template_ctx = {

		.event_attr = mcf_pmu_event_attrs,

	  .format_attr = cnvlink_pmu_format_attrs

		.format_attr = cnvlink_pmu_format_attrs,

		.filter_mask = NV_CNVL_FILTER_ID_MASK,

		.filter_default_val = NV_CNVL_FILTER_ID_MASK,

		.filter2_mask = 0x0,

		.filter2_default_val = 0x0,

		.get_filter = nv_cspmu_event_filter,

		.get_filter2 = NULL,

		.data = NULL,

		.init_data = NULL

	  },

	},

	{

	  .prodid = 0x2CF00000,

	  .prodid_mask = NV_PRODID_MASK,

	  .filter_mask = 0x0,

	  .filter_default_val = 0x0,

	  .name_pattern = "nvidia_scf_pmu_%u",

	  .name_fmt = NAME_FMT_SOCKET,

	  .template_ctx = {

		.event_attr = scf_pmu_event_attrs,

	  .format_attr = scf_pmu_format_attrs

		.format_attr = scf_pmu_format_attrs,

		.filter_mask = 0x0,

		.filter_default_val = 0x0,

		.filter2_mask = 0x0,

		.filter2_default_val = 0x0,

		.get_filter = nv_cspmu_event_filter,

		.get_filter2 = NULL,

		.data = NULL,

		.init_data = NULL

	  },

	},

	{

	  .prodid = 0,

	  .prodid_mask = 0,

	  .filter_mask = NV_GENERIC_FILTER_ID_MASK,

	  .filter_default_val = NV_GENERIC_FILTER_ID_MASK,

	  .name_pattern = "nvidia_uncore_pmu_%u",

	  .name_fmt = NAME_FMT_GENERIC,

	  .template_ctx = {

		.event_attr = generic_pmu_event_attrs,

	  .format_attr = generic_pmu_format_attrs

		.format_attr = generic_pmu_format_attrs,

		.filter_mask = NV_GENERIC_FILTER_ID_MASK,

		.filter_default_val = NV_GENERIC_FILTER_ID_MASK,

		.filter2_mask = NV_GENERIC_FILTER_ID_MASK,

		.filter2_default_val = NV_GENERIC_FILTER_ID_MASK,

		.get_filter = nv_cspmu_event_filter,

		.get_filter2 = nv_cspmu_event_filter2,

		.data = NULL,

		.init_data = NULL

	  },

	},

};
@@ -310,6 +391,14 @@ static char *nv_cspmu_format_name(const struct arm_cspmu *cspmu, 
	return name;

}



#define SET_OP(name, impl, match, default_op) \

	do { \

		if (match->ops.name) \

			impl->name = match->ops.name; \

		else if (default_op != NULL) \

			impl->name = default_op; \

	} while (false)



static int nv_cspmu_init_ops(struct arm_cspmu *cspmu)

{

	struct nv_cspmu_ctx *ctx;
@@ -330,20 +419,21 @@ static int nv_cspmu_init_ops(struct arm_cspmu *cspmu) 
			break;

	}



	/* Initialize the context with the matched template. */

	memcpy(ctx, &match->template_ctx, sizeof(struct nv_cspmu_ctx));

	ctx->name = nv_cspmu_format_name(cspmu, match);

	ctx->filter_mask	= match->filter_mask;

	ctx->filter_default_val = match->filter_default_val;

	ctx->event_attr		= match->event_attr;

	ctx->format_attr	= match->format_attr;



	cspmu->impl.ctx = ctx;



	/* NVIDIA specific callbacks. */

	impl_ops->set_cc_filter			= nv_cspmu_set_cc_filter;

	impl_ops->set_ev_filter			= nv_cspmu_set_ev_filter;

	impl_ops->get_event_attrs		= nv_cspmu_get_event_attrs;

	impl_ops->get_format_attrs		= nv_cspmu_get_format_attrs;

	impl_ops->get_name			= nv_cspmu_get_name;

	SET_OP(set_cc_filter, impl_ops, match, nv_cspmu_set_cc_filter);

	SET_OP(set_ev_filter, impl_ops, match, nv_cspmu_set_ev_filter);

	SET_OP(get_event_attrs, impl_ops, match, nv_cspmu_get_event_attrs);

	SET_OP(get_format_attrs, impl_ops, match, nv_cspmu_get_format_attrs);

	SET_OP(get_name, impl_ops, match, nv_cspmu_get_name);



	if (ctx->init_data)

		return ctx->init_data(cspmu);



	return 0;

}