Commit df68f4d8 authored by Anup Patel's avatar Anup Patel Committed by Anup Patel
Browse files

RISC-V: KVM: Allow Zicond extension for Guest/VM 



We extend the KVM ISA extension ONE_REG interface to allow KVM
user space to detect and enable Zicond extension for Guest/VM.

Signed-off-by: default avatarAnup Patel <apatel@ventanamicro.com>
Reviewed-by: default avatarAndrew Jones <ajones@ventanamicro.com>
Signed-off-by: default avatarAnup Patel <anup@brainfault.org>
parent 6a53a5fb

arch/riscv/include/uapi/asm/kvm.h

+1 −0
Original line number Diff line number Diff line
@@ -138,6 +138,7 @@ enum KVM_RISCV_ISA_EXT_ID { 
	KVM_RISCV_ISA_EXT_ZIFENCEI,

	KVM_RISCV_ISA_EXT_ZIHPM,

	KVM_RISCV_ISA_EXT_SMSTATEEN,

	KVM_RISCV_ISA_EXT_ZICOND,

	KVM_RISCV_ISA_EXT_MAX,

};

arch/riscv/kvm/vcpu_onereg.c

+2 −0
Original line number Diff line number Diff line
@@ -46,6 +46,7 @@ static const unsigned long kvm_isa_ext_arr[] = { 
	KVM_ISA_EXT_ARR(ZICBOM),

	KVM_ISA_EXT_ARR(ZICBOZ),

	KVM_ISA_EXT_ARR(ZICNTR),

	KVM_ISA_EXT_ARR(ZICOND),

	KVM_ISA_EXT_ARR(ZICSR),

	KVM_ISA_EXT_ARR(ZIFENCEI),

	KVM_ISA_EXT_ARR(ZIHINTPAUSE),
@@ -93,6 +94,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext) 
	case KVM_RISCV_ISA_EXT_ZBB:

	case KVM_RISCV_ISA_EXT_ZBS:

	case KVM_RISCV_ISA_EXT_ZICNTR:

	case KVM_RISCV_ISA_EXT_ZICOND:

	case KVM_RISCV_ISA_EXT_ZICSR:

	case KVM_RISCV_ISA_EXT_ZIFENCEI:

	case KVM_RISCV_ISA_EXT_ZIHINTPAUSE: