Commit e018f9f8 authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven
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clk: renesas: r9a09g056: Add clock and reset entries for WDT controllers 



Add module clock and reset definitions for WDT0-3, which are available
on the RZ/V2N (R9A09G056) SoC.

Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250513154635.273664-5-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent d3c25dd1

drivers/clk/renesas/r9a09g056-cpg.c

+20 −0
Original line number Diff line number Diff line
@@ -152,6 +152,22 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = { 
						BUS_MSTOP(11, BIT(15))),

	DEF_MOD("gtm_7_pclk",			CLK_PLLCLN_DIV16, 4, 10, 2, 10,

						BUS_MSTOP(12, BIT(0))),

	DEF_MOD("wdt_0_clkp",			CLK_PLLCM33_DIV16, 4, 11, 2, 11,

						BUS_MSTOP(3, BIT(10))),

	DEF_MOD("wdt_0_clk_loco",		CLK_QEXTAL, 4, 12, 2, 12,

						BUS_MSTOP(3, BIT(10))),

	DEF_MOD("wdt_1_clkp",			CLK_PLLCLN_DIV16, 4, 13, 2, 13,

						BUS_MSTOP(1, BIT(0))),

	DEF_MOD("wdt_1_clk_loco",		CLK_QEXTAL, 4, 14, 2, 14,

						BUS_MSTOP(1, BIT(0))),

	DEF_MOD("wdt_2_clkp",			CLK_PLLCLN_DIV16, 4, 15, 2, 15,

						BUS_MSTOP(5, BIT(12))),

	DEF_MOD("wdt_2_clk_loco",		CLK_QEXTAL, 5, 0, 2, 16,

						BUS_MSTOP(5, BIT(12))),

	DEF_MOD("wdt_3_clkp",			CLK_PLLCLN_DIV16, 5, 1, 2, 17,

						BUS_MSTOP(5, BIT(13))),

	DEF_MOD("wdt_3_clk_loco",		CLK_QEXTAL, 5, 2, 2, 18,

						BUS_MSTOP(5, BIT(13))),

	DEF_MOD("scif_0_clk_pck",		CLK_PLLCM33_DIV16, 8, 15, 4, 15,

						BUS_MSTOP(3, BIT(14))),

	DEF_MOD("riic_8_ckm",			CLK_PLLCM33_DIV16, 9, 3, 4, 19,
@@ -234,6 +250,10 @@ static const struct rzv2h_reset r9a09g056_resets[] __initconst = { 
	DEF_RST(7, 2, 3, 3),		/* GTM_5_PRESETZ */

	DEF_RST(7, 3, 3, 4),		/* GTM_6_PRESETZ */

	DEF_RST(7, 4, 3, 5),		/* GTM_7_PRESETZ */

	DEF_RST(7, 5, 3, 6),		/* WDT_0_RESET */

	DEF_RST(7, 6, 3, 7),		/* WDT_1_RESET */

	DEF_RST(7, 7, 3, 8),		/* WDT_2_RESET */

	DEF_RST(7, 8, 3, 9),		/* WDT_3_RESET */

	DEF_RST(9, 5, 4, 6),		/* SCIF_0_RST_SYSTEM_N */

	DEF_RST(9, 8, 4, 9),		/* RIIC_0_MRST */

	DEF_RST(9, 9, 4, 10),		/* RIIC_1_MRST */