Commit e1aa5ef8 authored by Huacai Chen's avatar Huacai Chen Committed by Jakub Kicinski
Browse files

net: stmmac: dwmac-loongson: Set clk_csr_i to 100-150MHz 



Current clk_csr_i setting of Loongson STMMAC (including LS7A1000/2000
and LS2K1000/2000/3000) are copy & paste from other drivers. In fact,
Loongson STMMAC use 125MHz clocks and need 62 freq division to within
2.5MHz, meeting most PHY MDC requirement. So fix by setting clk_csr_i
to 100-150MHz, otherwise some PHYs may link fail.

Cc: stable@vger.kernel.org
Fixes: 30bba69d ("stmmac: pci: Add dwmac support for Loongson")
Signed-off-by: default avatarHongliang Wang <wanghongliang@loongson.cn>
Signed-off-by: default avatarHuacai Chen <chenhuacai@loongson.cn>
Link: https://patch.msgid.link/20260203062901.2158236-1-chenhuacai@loongson.cn


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent c89477ad

drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c

+2 −2
Original line number Diff line number Diff line
@@ -91,8 +91,8 @@ static void loongson_default_data(struct pci_dev *pdev, 
	/* Get bus_id, this can be overwritten later */

	plat->bus_id = pci_dev_id(pdev);



	/* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */

	plat->clk_csr = STMMAC_CSR_20_35M;

	/* clk_csr_i = 100-150MHz & MDC = clk_csr_i/62 */

	plat->clk_csr = STMMAC_CSR_100_150M;

	plat->core_type = DWMAC_CORE_GMAC;

	plat->force_sf_dma_mode = 1;