Commit e2211387 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'qcom-clk-for-6.10' of... 

Merge tag 'qcom-clk-for-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom

Pull Qualcomm clk driver updates from Bjorn Andersson:

 - Add support in qcom RCG and RCG2 for multiple configurations for the same frequency
 - Use above support for IPQ8074 NSS port 5 and 6 clocks to resolve issues
 - Fix the Qualcomm APSS IPQ5018 PLL to fix boot failures of some boards
 - Cleanups and fixes for Qualcomm Stromer PLLs
 - Reduce max CPU frequency on Qualcomm APSS IPQ5018
 - Fix Kconfig dependencies of Qualcomm SM8650 GPU and SC8280XP camera
   clk drivers
 - Make Qualcomm MSM8998 Venus clocks functional
 - Cleanup downstream remnants related to DisplayPort across Qualcomm
   SM8450, SM6350, SM8550, and SM8650
 - Reuse the Huayra APSS register map on Qualcomm MSM8996 CBF PLL
 - Use a specific Qualcomm QCS404 compatible for the otherwise generic
   HFPLL
 - Remove Qualcomm SM8150 CPUSS AHB clk as it is unused
 - Remove an unused field in the Qualcomm RPM clk driver
 - Add missing MODULE_DEVICE_TABLE to Qualcomm MSM8917 and MSM8953
   global clock controller drivers

* tag 'qcom-clk-for-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (27 commits)
  clk: qcom: clk-alpha-pll: fix rate setting for Stromer PLLs
  clk: qcom: apss-ipq-pll: fix PLL rate for IPQ5018
  clk: qcom: Fix SM_GPUCC_8650 dependencies
  clk: qcom: Fix SC_CAMCC_8280XP dependencies
  clk: qcom: mmcc-msm8998: fix venus clock issue
  clk: qcom: dispcc-sm8650: fix DisplayPort clocks
  clk: qcom: dispcc-sm8550: fix DisplayPort clocks
  clk: qcom: dispcc-sm6350: fix DisplayPort clocks
  clk: qcom: dispcc-sm8450: fix DisplayPort clocks
  clk: qcom: clk-cbf-8996: use HUAYRA_APSS register map for cbf_pll
  clk: qcom: apss-ipq-pll: constify clk_init_data structures
  clk: qcom: apss-ipq-pll: constify match data structures
  clk: qcom: apss-ipq-pll: move Huayra register map to 'clk_alpha_pll_regs'
  clk: qcom: apss-ipq-pll: reuse Stromer reg offsets from 'clk_alpha_pll_regs'
  clk: qcom: apss-ipq-pll: use stromer ops for IPQ5018 to fix boot failure
  clk: qcom: gcc-ipq8074: rework nss_port5/6 clock to multiple conf
  clk: qcom: clk-rcg2: add support for rcg2 freq multi ops
  clk: qcom: clk-rcg: introduce support for multiple conf for same freq
  clk: qcom: hfpll: Add QCS404-specific compatible
  dt-bindings: clock: qcom,hfpll: Convert to YAML
  ...
parents 4cece764 3c5b3e17

Documentation/devicetree/bindings/clock/qcom,hfpll.txt

deleted100644 → 0
+0 −63
Original line number Diff line number Diff line 
High-Frequency PLL (HFPLL)



PROPERTIES



- compatible:

	Usage: required

	Value type: <string>:

		shall contain only one of the following. The generic

		compatible "qcom,hfpll" should be also included.



                        "qcom,hfpll-ipq8064", "qcom,hfpll"

                        "qcom,hfpll-apq8064", "qcom,hfpll"

                        "qcom,hfpll-msm8974", "qcom,hfpll"

                        "qcom,hfpll-msm8960", "qcom,hfpll"

                        "qcom,msm8976-hfpll-a53", "qcom,hfpll"

                        "qcom,msm8976-hfpll-a72", "qcom,hfpll"

                        "qcom,msm8976-hfpll-cci", "qcom,hfpll"



- reg:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: address and size of HPLL registers. An optional second

		    element specifies the address and size of the alias

		    register region.



- clocks:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: reference to the xo clock.



- clock-names:

	Usage: required

	Value type: <stringlist>

	Definition: must be "xo".



- clock-output-names:

	Usage: required

	Value type: <string>

	Definition: Name of the PLL. Typically hfpllX where X is a CPU number

		    starting at 0. Otherwise hfpll_Y where Y is more specific

		    such as "l2".



Example:



1) An HFPLL for the L2 cache.



	clock-controller@f9016000 {

		compatible = "qcom,hfpll-ipq8064", "qcom,hfpll";

		reg = <0xf9016000 0x30>;

		clocks = <&xo_board>;

		clock-names = "xo";

		clock-output-names = "hfpll_l2";

	};



2) An HFPLL for CPU0. This HFPLL has the alias register region.



	clock-controller@f908a000 {

		compatible = "qcom,hfpll-ipq8064", "qcom,hfpll";

		reg = <0xf908a000 0x30>, <0xf900a000 0x30>;

		clocks = <&xo_board>;

		clock-names = "xo";

		clock-output-names = "hfpll0";

	};

Documentation/devicetree/bindings/clock/qcom,hfpll.yaml

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+69 −0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,hfpll.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm High-Frequency PLL



maintainers:

  - Bjorn Andersson <andersson@kernel.org>



description:

  The HFPLL is used as CPU PLL on various Qualcomm SoCs.



properties:

  compatible:

    oneOf:

      - enum:

          - qcom,msm8974-hfpll

          - qcom,msm8976-hfpll-a53

          - qcom,msm8976-hfpll-a72

          - qcom,msm8976-hfpll-cci

          - qcom,qcs404-hfpll

      - const: qcom,hfpll

        deprecated: true



  reg:

    items:

      - description: HFPLL registers

      - description: Alias register region

    minItems: 1



  '#clock-cells':

    const: 0



  clocks:

    items:

      - description: board XO clock



  clock-names:

    items:

      - const: xo



  clock-output-names:

    description:

      Name of the PLL. Typically hfpllX where X is a CPU number starting at 0.

      Otherwise hfpll_Y where Y is more specific such as "l2".

    maxItems: 1



required:

  - compatible

  - reg

  - '#clock-cells'

  - clocks

  - clock-names

  - clock-output-names



additionalProperties: false



examples:

  - |

    clock-controller@f908a000 {

        compatible = "qcom,msm8974-hfpll";

        reg = <0xf908a000 0x30>, <0xf900a000 0x30>;

        #clock-cells = <0>;

        clock-output-names = "hfpll0";

        clocks = <&xo_board>;

        clock-names = "xo";

    };

drivers/clk/qcom/Kconfig

+2 −0
Original line number Diff line number Diff line
@@ -474,6 +474,7 @@ config SC_CAMCC_7280 


config SC_CAMCC_8280XP

	tristate "SC8280XP Camera Clock Controller"

	depends on ARM64 || COMPILE_TEST

	select SC_GCC_8280XP

	help

	  Support for the camera clock controller on Qualcomm Technologies, Inc
@@ -1094,6 +1095,7 @@ config SM_GPUCC_8550 


config SM_GPUCC_8650

	tristate "SM8650 Graphics Clock Controller"

	depends on ARM64 || COMPILE_TEST

	select SM_GCC_8650

	help

	  Support for the graphics clock controller on SM8650 devices.

drivers/clk/qcom/apss-ipq-pll.c

+35 −40
Original line number Diff line number Diff line
@@ -8,61 +8,54 @@ 


#include "clk-alpha-pll.h"



/*

 * Even though APSS PLL type is of existing one (like Huayra), its offsets

 * are different from the one mentioned in the clk-alpha-pll.c, since the

 * PLL is specific to APSS, so lets the define the same.

 */

static const u8 ipq_pll_offsets[][PLL_OFF_MAX_REGS] = {

	[CLK_ALPHA_PLL_TYPE_HUAYRA] =  {

		[PLL_OFF_L_VAL] = 0x08,

		[PLL_OFF_ALPHA_VAL] = 0x10,

		[PLL_OFF_USER_CTL] = 0x18,

		[PLL_OFF_CONFIG_CTL] = 0x20,

		[PLL_OFF_CONFIG_CTL_U] = 0x24,

		[PLL_OFF_STATUS] = 0x28,

		[PLL_OFF_TEST_CTL] = 0x30,

		[PLL_OFF_TEST_CTL_U] = 0x34,

static struct clk_alpha_pll ipq_pll_huayra = {

	.offset = 0x0,

	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA_APSS],

	.flags = SUPPORTS_DYNAMIC_UPDATE,

	.clkr = {

		.enable_reg = 0x0,

		.enable_mask = BIT(0),

		.hw.init = &(const struct clk_init_data) {

			.name = "a53pll",

			.parent_data = &(const struct clk_parent_data) {

				.fw_name = "xo",

			},

			.num_parents = 1,

			.ops = &clk_alpha_pll_huayra_ops,

		},

	[CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = {

		[PLL_OFF_L_VAL] = 0x08,

		[PLL_OFF_ALPHA_VAL] = 0x10,

		[PLL_OFF_ALPHA_VAL_U] = 0x14,

		[PLL_OFF_USER_CTL] = 0x18,

		[PLL_OFF_USER_CTL_U] = 0x1c,

		[PLL_OFF_CONFIG_CTL] = 0x20,

		[PLL_OFF_STATUS] = 0x28,

		[PLL_OFF_TEST_CTL] = 0x30,

		[PLL_OFF_TEST_CTL_U] = 0x34,

	},

};



static struct clk_alpha_pll ipq_pll_huayra = {

static struct clk_alpha_pll ipq_pll_stromer = {

	.offset = 0x0,

	.regs = ipq_pll_offsets[CLK_ALPHA_PLL_TYPE_HUAYRA],

	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER],

	.flags = SUPPORTS_DYNAMIC_UPDATE,

	.clkr = {

		.enable_reg = 0x0,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

		.hw.init = &(const struct clk_init_data) {

			.name = "a53pll",

			.parent_data = &(const struct clk_parent_data) {

				.fw_name = "xo",

			},

			.num_parents = 1,

			.ops = &clk_alpha_pll_huayra_ops,

			.ops = &clk_alpha_pll_stromer_ops,

		},

	},

};



static struct clk_alpha_pll ipq_pll_stromer_plus = {

	.offset = 0x0,

	.regs = ipq_pll_offsets[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],

	/*

	 * The register offsets of the Stromer Plus PLL used in IPQ5332

	 * are the same as the Stromer PLL's offsets.

	 */

	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER],

	.flags = SUPPORTS_DYNAMIC_UPDATE,

	.clkr = {

		.enable_reg = 0x0,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

		.hw.init = &(const struct clk_init_data) {

			.name = "a53pll",

			.parent_data = &(const struct clk_parent_data) {

				.fw_name = "xo",
@@ -73,8 +66,9 @@ static struct clk_alpha_pll ipq_pll_stromer_plus = { 
	},

};



/* 1.008 GHz configuration */

static const struct alpha_pll_config ipq5018_pll_config = {

	.l = 0x32,

	.l = 0x2a,

	.config_ctl_val = 0x4001075b,

	.config_ctl_hi_val = 0x304,

	.main_output_mask = BIT(0),
@@ -144,30 +138,30 @@ struct apss_pll_data { 
};



static const struct apss_pll_data ipq5018_pll_data = {

	.pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS,

	.pll = &ipq_pll_stromer_plus,

	.pll_type = CLK_ALPHA_PLL_TYPE_STROMER,

	.pll = &ipq_pll_stromer,

	.pll_config = &ipq5018_pll_config,

};



static struct apss_pll_data ipq5332_pll_data = {

static const struct apss_pll_data ipq5332_pll_data = {

	.pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS,

	.pll = &ipq_pll_stromer_plus,

	.pll_config = &ipq5332_pll_config,

};



static struct apss_pll_data ipq8074_pll_data = {

static const struct apss_pll_data ipq8074_pll_data = {

	.pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA,

	.pll = &ipq_pll_huayra,

	.pll_config = &ipq8074_pll_config,

};



static struct apss_pll_data ipq6018_pll_data = {

static const struct apss_pll_data ipq6018_pll_data = {

	.pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA,

	.pll = &ipq_pll_huayra,

	.pll_config = &ipq6018_pll_config,

};



static struct apss_pll_data ipq9574_pll_data = {

static const struct apss_pll_data ipq9574_pll_data = {

	.pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA,

	.pll = &ipq_pll_huayra,

	.pll_config = &ipq9574_pll_config,
@@ -203,7 +197,8 @@ static int apss_ipq_pll_probe(struct platform_device *pdev) 


	if (data->pll_type == CLK_ALPHA_PLL_TYPE_HUAYRA)

		clk_alpha_pll_configure(data->pll, regmap, data->pll_config);

	else if (data->pll_type == CLK_ALPHA_PLL_TYPE_STROMER_PLUS)

	else if (data->pll_type == CLK_ALPHA_PLL_TYPE_STROMER ||

		 data->pll_type == CLK_ALPHA_PLL_TYPE_STROMER_PLUS)

		clk_stromer_pll_configure(data->pll, regmap, data->pll_config);



	ret = devm_clk_register_regmap(dev, &data->pll->clkr);

drivers/clk/qcom/clk-alpha-pll.c

+22 −2
Original line number Diff line number Diff line
@@ -83,6 +83,16 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { 
		[PLL_OFF_TEST_CTL_U] = 0x20,

		[PLL_OFF_STATUS] = 0x24,

	},

	[CLK_ALPHA_PLL_TYPE_HUAYRA_APSS] =  {

		[PLL_OFF_L_VAL] = 0x08,

		[PLL_OFF_ALPHA_VAL] = 0x10,

		[PLL_OFF_USER_CTL] = 0x18,

		[PLL_OFF_CONFIG_CTL] = 0x20,

		[PLL_OFF_CONFIG_CTL_U] = 0x24,

		[PLL_OFF_STATUS] = 0x28,

		[PLL_OFF_TEST_CTL] = 0x30,

		[PLL_OFF_TEST_CTL_U] = 0x34,

	},

	[CLK_ALPHA_PLL_TYPE_BRAMMO] =  {

		[PLL_OFF_L_VAL] = 0x04,

		[PLL_OFF_ALPHA_VAL] = 0x08,
@@ -213,10 +223,9 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { 
		[PLL_OFF_USER_CTL] = 0x18,

		[PLL_OFF_USER_CTL_U] = 0x1c,

		[PLL_OFF_CONFIG_CTL] = 0x20,

		[PLL_OFF_CONFIG_CTL_U] = 0xff,

		[PLL_OFF_STATUS] = 0x28,

		[PLL_OFF_TEST_CTL] = 0x30,

		[PLL_OFF_TEST_CTL_U] = 0x34,

		[PLL_OFF_STATUS] = 0x28,

	},

	[CLK_ALPHA_PLL_TYPE_STROMER_PLUS] =  {

		[PLL_OFF_L_VAL] = 0x04,
@@ -2114,6 +2123,15 @@ void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regma 
{

	u32 lval = config->l;



	/*

	 * If the bootloader left the PLL enabled it's likely that there are

	 * RCGs that will lock up if we disable the PLL below.

	 */

	if (trion_pll_is_enabled(pll, regmap)) {

		pr_debug("Lucid Evo PLL is already enabled, skipping configuration\n");

		return;

	}



	lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT;

	clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval);

	clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
@@ -2490,6 +2508,8 @@ static int clk_alpha_pll_stromer_set_rate(struct clk_hw *hw, unsigned long rate, 
	rate = alpha_pll_round_rate(rate, prate, &l, &a, ALPHA_REG_BITWIDTH);



	regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);



	a <<= ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH;

	regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);

	regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),

		     a >> ALPHA_BITWIDTH);