Loading .mailmap +7 −0 Original line number Diff line number Diff line Loading @@ -325,6 +325,7 @@ Kenneth W Chen <kenneth.w.chen@intel.com> Kenneth Westfield <quic_kwestfie@quicinc.com> <kwestfie@codeaurora.org> Kiran Gunda <quic_kgunda@quicinc.com> <kgunda@codeaurora.org> Kirill Tkhai <tkhai@ya.ru> <ktkhai@virtuozzo.com> Kishon Vijay Abraham I <kishon@kernel.org> <kishon@ti.com> Konstantin Khlebnikov <koct9i@gmail.com> <khlebnikov@yandex-team.ru> Konstantin Khlebnikov <koct9i@gmail.com> <k.khlebnikov@samsung.com> Koushik <raghavendra.koushik@neterion.com> Loading Loading @@ -553,6 +554,7 @@ Senthilkumar N L <quic_snlakshm@quicinc.com> <snlakshm@codeaurora.org> Serge Hallyn <sergeh@kernel.org> <serge.hallyn@canonical.com> Serge Hallyn <sergeh@kernel.org> <serue@us.ibm.com> Seth Forshee <sforshee@kernel.org> <seth.forshee@canonical.com> Shakeel Butt <shakeel.butt@linux.dev> <shakeelb@google.com> Shannon Nelson <shannon.nelson@amd.com> <snelson@pensando.io> Shannon Nelson <shannon.nelson@amd.com> <shannon.nelson@intel.com> Shannon Nelson <shannon.nelson@amd.com> <shannon.nelson@oracle.com> Loading Loading @@ -608,6 +610,11 @@ TripleX Chung <xxx.phy@gmail.com> <triplex@zh-kernel.org> TripleX Chung <xxx.phy@gmail.com> <zhongyu@18mail.cn> Tsuneo Yoshioka <Tsuneo.Yoshioka@f-secure.com> Tudor Ambarus <tudor.ambarus@linaro.org> <tudor.ambarus@microchip.com> Tvrtko Ursulin <tursulin@ursulin.net> <tvrtko.ursulin@intel.com> Tvrtko Ursulin <tursulin@ursulin.net> <tvrtko.ursulin@linux.intel.com> Tvrtko Ursulin <tursulin@ursulin.net> <tvrtko.ursulin@sophos.com> Tvrtko Ursulin <tursulin@ursulin.net> <tvrtko.ursulin@onelan.co.uk> Tvrtko Ursulin <tursulin@ursulin.net> <tvrtko@ursulin.net> Tycho Andersen <tycho@tycho.pizza> <tycho@tycho.ws> Tzung-Bi Shih <tzungbi@kernel.org> <tzungbi@google.com> Uwe Kleine-König <ukleinek@informatik.uni-freiburg.de> Loading Documentation/arch/x86/mds.rst +27 −11 Original line number Diff line number Diff line Loading @@ -95,6 +95,9 @@ The kernel provides a function to invoke the buffer clearing: mds_clear_cpu_buffers() Also macro CLEAR_CPU_BUFFERS can be used in ASM late in exit-to-user path. Other than CFLAGS.ZF, this macro doesn't clobber any registers. The mitigation is invoked on kernel/userspace, hypervisor/guest and C-state (idle) transitions. Loading Loading @@ -138,17 +141,30 @@ Mitigation points When transitioning from kernel to user space the CPU buffers are flushed on affected CPUs when the mitigation is not disabled on the kernel command line. The migitation is enabled through the static key mds_user_clear. The mitigation is invoked in prepare_exit_to_usermode() which covers all but one of the kernel to user space transitions. The exception is when we return from a Non Maskable Interrupt (NMI), which is handled directly in do_nmi(). (The reason that NMI is special is that prepare_exit_to_usermode() can enable IRQs. In NMI context, NMIs are blocked, and we don't want to enable IRQs with NMIs blocked.) command line. The mitigation is enabled through the feature flag X86_FEATURE_CLEAR_CPU_BUF. The mitigation is invoked just before transitioning to userspace after user registers are restored. This is done to minimize the window in which kernel data could be accessed after VERW e.g. via an NMI after VERW. **Corner case not handled** Interrupts returning to kernel don't clear CPUs buffers since the exit-to-user path is expected to do that anyways. But, there could be a case when an NMI is generated in kernel after the exit-to-user path has cleared the buffers. This case is not handled and NMI returning to kernel don't clear CPU buffers because: 1. It is rare to get an NMI after VERW, but before returning to userspace. 2. For an unprivileged user, there is no known way to make that NMI less rare or target it. 3. It would take a large number of these precisely-timed NMIs to mount an actual attack. There's presumably not enough bandwidth. 4. The NMI in question occurs after a VERW, i.e. when user state is restored and most interesting data is already scrubbed. Whats left is only the data that NMI touches, and that may or may not be of any interest. 2. C-State transition Loading Documentation/conf.py +6 −0 Original line number Diff line number Diff line Loading @@ -388,6 +388,12 @@ latex_elements = { verbatimhintsturnover=false, ''', # # Some of our authors are fond of deep nesting; tell latex to # cope. # 'maxlistdepth': '10', # For CJK One-half spacing, need to be in front of hyperref 'extrapackages': r'\usepackage{setspace}', Loading Documentation/devicetree/bindings/clock/google,gs101-clock.yaml +2 −2 Original line number Diff line number Diff line Loading @@ -85,8 +85,8 @@ allOf: clock-names: items: - const: dout_cmu_misc_bus - const: dout_cmu_misc_sss - const: bus - const: sss additionalProperties: false Loading Documentation/devicetree/bindings/net/renesas,ethertsn.yaml +2 −0 Original line number Diff line number Diff line Loading @@ -65,9 +65,11 @@ properties: rx-internal-delay-ps: enum: [0, 1800] default: 0 tx-internal-delay-ps: enum: [0, 2000] default: 0 '#address-cells': const: 1 Loading Loading
.mailmap +7 −0 Original line number Diff line number Diff line Loading @@ -325,6 +325,7 @@ Kenneth W Chen <kenneth.w.chen@intel.com> Kenneth Westfield <quic_kwestfie@quicinc.com> <kwestfie@codeaurora.org> Kiran Gunda <quic_kgunda@quicinc.com> <kgunda@codeaurora.org> Kirill Tkhai <tkhai@ya.ru> <ktkhai@virtuozzo.com> Kishon Vijay Abraham I <kishon@kernel.org> <kishon@ti.com> Konstantin Khlebnikov <koct9i@gmail.com> <khlebnikov@yandex-team.ru> Konstantin Khlebnikov <koct9i@gmail.com> <k.khlebnikov@samsung.com> Koushik <raghavendra.koushik@neterion.com> Loading Loading @@ -553,6 +554,7 @@ Senthilkumar N L <quic_snlakshm@quicinc.com> <snlakshm@codeaurora.org> Serge Hallyn <sergeh@kernel.org> <serge.hallyn@canonical.com> Serge Hallyn <sergeh@kernel.org> <serue@us.ibm.com> Seth Forshee <sforshee@kernel.org> <seth.forshee@canonical.com> Shakeel Butt <shakeel.butt@linux.dev> <shakeelb@google.com> Shannon Nelson <shannon.nelson@amd.com> <snelson@pensando.io> Shannon Nelson <shannon.nelson@amd.com> <shannon.nelson@intel.com> Shannon Nelson <shannon.nelson@amd.com> <shannon.nelson@oracle.com> Loading Loading @@ -608,6 +610,11 @@ TripleX Chung <xxx.phy@gmail.com> <triplex@zh-kernel.org> TripleX Chung <xxx.phy@gmail.com> <zhongyu@18mail.cn> Tsuneo Yoshioka <Tsuneo.Yoshioka@f-secure.com> Tudor Ambarus <tudor.ambarus@linaro.org> <tudor.ambarus@microchip.com> Tvrtko Ursulin <tursulin@ursulin.net> <tvrtko.ursulin@intel.com> Tvrtko Ursulin <tursulin@ursulin.net> <tvrtko.ursulin@linux.intel.com> Tvrtko Ursulin <tursulin@ursulin.net> <tvrtko.ursulin@sophos.com> Tvrtko Ursulin <tursulin@ursulin.net> <tvrtko.ursulin@onelan.co.uk> Tvrtko Ursulin <tursulin@ursulin.net> <tvrtko@ursulin.net> Tycho Andersen <tycho@tycho.pizza> <tycho@tycho.ws> Tzung-Bi Shih <tzungbi@kernel.org> <tzungbi@google.com> Uwe Kleine-König <ukleinek@informatik.uni-freiburg.de> Loading
Documentation/arch/x86/mds.rst +27 −11 Original line number Diff line number Diff line Loading @@ -95,6 +95,9 @@ The kernel provides a function to invoke the buffer clearing: mds_clear_cpu_buffers() Also macro CLEAR_CPU_BUFFERS can be used in ASM late in exit-to-user path. Other than CFLAGS.ZF, this macro doesn't clobber any registers. The mitigation is invoked on kernel/userspace, hypervisor/guest and C-state (idle) transitions. Loading Loading @@ -138,17 +141,30 @@ Mitigation points When transitioning from kernel to user space the CPU buffers are flushed on affected CPUs when the mitigation is not disabled on the kernel command line. The migitation is enabled through the static key mds_user_clear. The mitigation is invoked in prepare_exit_to_usermode() which covers all but one of the kernel to user space transitions. The exception is when we return from a Non Maskable Interrupt (NMI), which is handled directly in do_nmi(). (The reason that NMI is special is that prepare_exit_to_usermode() can enable IRQs. In NMI context, NMIs are blocked, and we don't want to enable IRQs with NMIs blocked.) command line. The mitigation is enabled through the feature flag X86_FEATURE_CLEAR_CPU_BUF. The mitigation is invoked just before transitioning to userspace after user registers are restored. This is done to minimize the window in which kernel data could be accessed after VERW e.g. via an NMI after VERW. **Corner case not handled** Interrupts returning to kernel don't clear CPUs buffers since the exit-to-user path is expected to do that anyways. But, there could be a case when an NMI is generated in kernel after the exit-to-user path has cleared the buffers. This case is not handled and NMI returning to kernel don't clear CPU buffers because: 1. It is rare to get an NMI after VERW, but before returning to userspace. 2. For an unprivileged user, there is no known way to make that NMI less rare or target it. 3. It would take a large number of these precisely-timed NMIs to mount an actual attack. There's presumably not enough bandwidth. 4. The NMI in question occurs after a VERW, i.e. when user state is restored and most interesting data is already scrubbed. Whats left is only the data that NMI touches, and that may or may not be of any interest. 2. C-State transition Loading
Documentation/conf.py +6 −0 Original line number Diff line number Diff line Loading @@ -388,6 +388,12 @@ latex_elements = { verbatimhintsturnover=false, ''', # # Some of our authors are fond of deep nesting; tell latex to # cope. # 'maxlistdepth': '10', # For CJK One-half spacing, need to be in front of hyperref 'extrapackages': r'\usepackage{setspace}', Loading
Documentation/devicetree/bindings/clock/google,gs101-clock.yaml +2 −2 Original line number Diff line number Diff line Loading @@ -85,8 +85,8 @@ allOf: clock-names: items: - const: dout_cmu_misc_bus - const: dout_cmu_misc_sss - const: bus - const: sss additionalProperties: false Loading
Documentation/devicetree/bindings/net/renesas,ethertsn.yaml +2 −0 Original line number Diff line number Diff line Loading @@ -65,9 +65,11 @@ properties: rx-internal-delay-ps: enum: [0, 1800] default: 0 tx-internal-delay-ps: enum: [0, 2000] default: 0 '#address-cells': const: 1 Loading