Commit e3493d68 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2022-10-28' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "Regularly scheduled fixes for drm, live from a Red Hat office for the
  first time in a while.

  The core has two fixes, one for scheduler leak and one for aperture
  uninit read.

  Otherwise a single bridge fix, and msm, amdgpu/kfd and i915 have a set
  of fixes each.

  sched:
   - Stop leaking fences when killing a sched entity.

  aperture:
   - Avoid uninitialized read in aperture_remove_conflicting_pci_device()

  bridge:
   - Fix HPD on bridge/ps8640.

  msm:
   - Fix shrinker deadlock
   - Fix crash during suspend after unbind
   - Fix IRQ lifetime issues
   - Fix potential memory corruption with too many bridges
   - Fix memory corruption on GPU state capture

  amdgpu:
   - Stable pstate fix
   - SMU 13.x updates
   - SR-IOV fixes
   - PCI AER fix
   - GC 11.x fixes
   - Display fixes
   - Expose IMU firmware version for debugging
   - Plane modifier fix
   - S0i3 fix

  amdkfd:
   - Fix possible memory leak
   - Fix GC 10.x cache info reporting

  i915:
   - Extend Wa_1607297627 to Alderlake-P
   - Keep PCI autosuspend control 'on' by default on all dGPU
   - Reset frl trained flag before restarting FRL training"

* tag 'drm-fixes-2022-10-28' of git://anongit.freedesktop.org/drm/drm: (39 commits)
  fbdev/core: Avoid uninitialized read in aperture_remove_conflicting_pci_device()
  drm/amdgpu: disallow gfxoff until GC IP blocks complete s2idle resume
  drm/scheduler: fix fence ref counting
  drm/amd/display: Revert logic for plane modifiers
  drm/amdkfd: correct the cache info for gfx1036
  drm/amdkfd: update gfx1037 Lx cache setting
  drm/amdgpu: skip mes self test for gc 11.0.3 in recover
  drm/amd: Add IMU fw version to fw version queries
  drm/amd/display: Don't return false if no stream
  drm/amd/display: Remove wrong pipe control lock
  drm/amd/pm: allow gfxoff on gc_11_0_3
  drm/amdkfd: Fix memory leak in kfd_mem_dmamap_userptr()
  drm/amdgpu: Remove ATC L2 access for MMHUB 2.1.x
  drm/i915/dp: Reset frl trained flag before restarting FRL training
  drm/i915/dgfx: Keep PCI autosuspend control 'on' by default on all dGPU
  drm/i915: Extend Wa_1607297627 to Alderlake-P
  drm/amdgpu: Adjust MES polling timeout for sriov
  drm/amd/pm: update driver-if header for smu_v13_0_10
  drm/amdgpu: fix pstate setting issue
  drm/bridge: ps8640: Add back the 50 ms mystery delay after HPD
  ...
parents 05c31d25 b2196401

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

+3 −3
Original line number Diff line number Diff line
@@ -510,13 +510,13 @@ kfd_mem_dmamap_userptr(struct kgd_mem *mem, 
	struct ttm_tt *ttm = bo->tbo.ttm;

	int ret;



	if (WARN_ON(ttm->num_pages != src_ttm->num_pages))

		return -EINVAL;



	ttm->sg = kmalloc(sizeof(*ttm->sg), GFP_KERNEL);

	if (unlikely(!ttm->sg))

		return -ENOMEM;



	if (WARN_ON(ttm->num_pages != src_ttm->num_pages))

		return -EINVAL;



	/* Same sequence as in amdgpu_ttm_tt_pin_userptr */

	ret = sg_alloc_table_from_pages(ttm->sg, src_ttm->pages,

					ttm->num_pages, 0,

drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c

+4 −1
Original line number Diff line number Diff line
@@ -326,6 +326,9 @@ static int amdgpu_ctx_init(struct amdgpu_ctx_mgr *mgr, int32_t priority, 
	if (r)

		return r;



	if (mgr->adev->pm.stable_pstate_ctx)

		ctx->stable_pstate = mgr->adev->pm.stable_pstate_ctx->stable_pstate;

	else

		ctx->stable_pstate = current_stable_pstate;



	return 0;

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+17 −1
Original line number Diff line number Diff line
@@ -3210,6 +3210,15 @@ static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev) 
			return r;

		}

		adev->ip_blocks[i].status.hw = true;



		if (adev->in_s0ix && adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {

			/* disable gfxoff for IP resume. The gfxoff will be re-enabled in

			 * amdgpu_device_resume() after IP resume.

			 */

			amdgpu_gfx_off_ctrl(adev, false);

			DRM_DEBUG("will disable gfxoff for re-initializing other blocks\n");

		}



	}



	return 0;
@@ -4185,6 +4194,13 @@ int amdgpu_device_resume(struct drm_device *dev, bool fbcon) 
	/* Make sure IB tests flushed */

	flush_delayed_work(&adev->delayed_init_work);



	if (adev->in_s0ix) {

		/* re-enable gfxoff after IP resume. This re-enables gfxoff after

		 * it was disabled for IP resume in amdgpu_device_ip_resume_phase2().

		 */

		amdgpu_gfx_off_ctrl(adev, true);

		DRM_DEBUG("will enable gfxoff for the mission mode\n");

	}

	if (fbcon)

		drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, false);
@@ -5381,7 +5397,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 
			drm_sched_start(&ring->sched, !tmp_adev->asic_reset_res);

		}



		if (adev->enable_mes)

		if (adev->enable_mes && adev->ip_versions[GC_HWIP][0] != IP_VERSION(11, 0, 3))

			amdgpu_mes_self_test(tmp_adev);



		if (!drm_drv_uses_atomic_modeset(adev_to_drm(tmp_adev)) && !job_signaled) {

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

+13 −0
Original line number Diff line number Diff line
@@ -344,6 +344,10 @@ static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 
		fw_info->ver = adev->mes.ucode_fw_version[1];

		fw_info->feature = 0;

		break;

	case AMDGPU_INFO_FW_IMU:

		fw_info->ver = adev->gfx.imu_fw_version;

		fw_info->feature = 0;

		break;

	default:

		return -EINVAL;

	}
@@ -1520,6 +1524,15 @@ static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused) 
			   fw_info.feature, fw_info.ver);

	}



	/* IMU */

	query_fw.fw_type = AMDGPU_INFO_FW_IMU;

	query_fw.index = 0;

	ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);

	if (ret)

		return ret;

	seq_printf(m, "IMU feature version: %u, firmware version: 0x%08x\n",

		   fw_info.feature, fw_info.ver);



	/* PSP SOS */

	query_fw.fw_type = AMDGPU_INFO_FW_SOS;

	ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);

drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c

+3 −1
Original line number Diff line number Diff line
@@ -698,6 +698,7 @@ FW_VERSION_ATTR(rlc_srlg_fw_version, 0444, gfx.rlc_srlg_fw_version); 
FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version);

FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version);

FW_VERSION_ATTR(mec2_fw_version, 0444, gfx.mec2_fw_version);

FW_VERSION_ATTR(imu_fw_version, 0444, gfx.imu_fw_version);

FW_VERSION_ATTR(sos_fw_version, 0444, psp.sos.fw_version);

FW_VERSION_ATTR(asd_fw_version, 0444, psp.asd_context.bin_desc.fw_version);

FW_VERSION_ATTR(ta_ras_fw_version, 0444, psp.ras_context.context.bin_desc.fw_version);
@@ -719,7 +720,8 @@ static struct attribute *fw_attrs[] = { 
	&dev_attr_ta_ras_fw_version.attr, &dev_attr_ta_xgmi_fw_version.attr,

	&dev_attr_smc_fw_version.attr, &dev_attr_sdma_fw_version.attr,

	&dev_attr_sdma2_fw_version.attr, &dev_attr_vcn_fw_version.attr,

	&dev_attr_dmcu_fw_version.attr, NULL

	&dev_attr_dmcu_fw_version.attr, &dev_attr_imu_fw_version.attr,

	NULL

};



static const struct attribute_group fw_attr_group = {