Unverified Commit e3f1fe98 authored by Shyam Sundar S K's avatar Shyam Sundar S K Committed by Ilpo Järvinen
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platform/x86/amd/pmc: Move macros and structures to the PMC header file 



To improve the code organization and readability, move the macros and
structures from the AMD PMC driver to the PMC header file.

Co-developed-by: default avatarSanket Goswami <Sanket.Goswami@amd.com>
Signed-off-by: default avatarSanket Goswami <Sanket.Goswami@amd.com>
Signed-off-by: default avatarShyam Sundar S K <Shyam-sundar.S-k@amd.com>
Link: https://lore.kernel.org/r/20250305142615.410178-2-Shyam-sundar.S-k@amd.com


Reviewed-by: default avatarIlpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: default avatarIlpo Järvinen <ilpo.jarvinen@linux.intel.com>
parent 351f3d9a

drivers/platform/x86/amd/pmc/pmc.c

+0 −81
Original line number Diff line number Diff line
@@ -32,70 +32,6 @@ 


#include "pmc.h"



/* SMU communication registers */

#define AMD_PMC_REGISTER_RESPONSE	0x980

#define AMD_PMC_REGISTER_ARGUMENT	0x9BC



/* PMC Scratch Registers */

#define AMD_PMC_SCRATCH_REG_CZN		0x94

#define AMD_PMC_SCRATCH_REG_YC		0xD14

#define AMD_PMC_SCRATCH_REG_1AH		0xF14



/* STB Registers */

#define AMD_PMC_STB_S2IDLE_PREPARE	0xC6000001

#define AMD_PMC_STB_S2IDLE_RESTORE	0xC6000002

#define AMD_PMC_STB_S2IDLE_CHECK	0xC6000003



/* Base address of SMU for mapping physical address to virtual address */

#define AMD_PMC_MAPPING_SIZE		0x01000

#define AMD_PMC_BASE_ADDR_OFFSET	0x10000

#define AMD_PMC_BASE_ADDR_LO		0x13B102E8

#define AMD_PMC_BASE_ADDR_HI		0x13B102EC

#define AMD_PMC_BASE_ADDR_LO_MASK	GENMASK(15, 0)

#define AMD_PMC_BASE_ADDR_HI_MASK	GENMASK(31, 20)



/* SMU Response Codes */

#define AMD_PMC_RESULT_OK                    0x01

#define AMD_PMC_RESULT_CMD_REJECT_BUSY       0xFC

#define AMD_PMC_RESULT_CMD_REJECT_PREREQ     0xFD

#define AMD_PMC_RESULT_CMD_UNKNOWN           0xFE

#define AMD_PMC_RESULT_FAILED                0xFF



/* FCH SSC Registers */

#define FCH_S0I3_ENTRY_TIME_L_OFFSET	0x30

#define FCH_S0I3_ENTRY_TIME_H_OFFSET	0x34

#define FCH_S0I3_EXIT_TIME_L_OFFSET	0x38

#define FCH_S0I3_EXIT_TIME_H_OFFSET	0x3C

#define FCH_SSC_MAPPING_SIZE		0x800

#define FCH_BASE_PHY_ADDR_LOW		0xFED81100

#define FCH_BASE_PHY_ADDR_HIGH		0x00000000



/* SMU Message Definations */

#define SMU_MSG_GETSMUVERSION		0x02

#define SMU_MSG_LOG_GETDRAM_ADDR_HI	0x04

#define SMU_MSG_LOG_GETDRAM_ADDR_LO	0x05

#define SMU_MSG_LOG_START		0x06

#define SMU_MSG_LOG_RESET		0x07

#define SMU_MSG_LOG_DUMP_DATA		0x08

#define SMU_MSG_GET_SUP_CONSTRAINTS	0x09



#define PMC_MSG_DELAY_MIN_US		50

#define RESPONSE_REGISTER_LOOP_MAX	20000



#define DELAY_MIN_US		2000

#define DELAY_MAX_US		3000



enum amd_pmc_def {

	MSG_TEST = 0x01,

	MSG_OS_HINT_PCO,

	MSG_OS_HINT_RN,

};



struct amd_pmc_bit_map {

	const char *name;

	u32 bit_mask;

};



static const struct amd_pmc_bit_map soc15_ip_blk_v2[] = {

	{"DISPLAY",     BIT(0)},

	{"CPU",         BIT(1)},
@@ -165,23 +101,6 @@ static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u3 
	iowrite32(val, dev->regbase + reg_offset);

}



struct smu_metrics {

	u32 table_version;

	u32 hint_count;

	u32 s0i3_last_entry_status;

	u32 timein_s0i2;

	u64 timeentering_s0i3_lastcapture;

	u64 timeentering_s0i3_totaltime;

	u64 timeto_resume_to_os_lastcapture;

	u64 timeto_resume_to_os_totaltime;

	u64 timein_s0i3_lastcapture;

	u64 timein_s0i3_totaltime;

	u64 timein_swdrips_lastcapture;

	u64 timein_swdrips_totaltime;

	u64 timecondition_notmet_lastcapture[32];

	u64 timecondition_notmet_totaltime[32];

} __packed;



static void amd_pmc_get_ip_info(struct amd_pmc_dev *dev)

{

	switch (dev->cpu_id) {

drivers/platform/x86/amd/pmc/pmc.h

+81 −0
Original line number Diff line number Diff line
@@ -14,6 +14,59 @@ 
#include <linux/types.h>

#include <linux/mutex.h>



/* SMU communication registers */

#define AMD_PMC_REGISTER_RESPONSE	0x980

#define AMD_PMC_REGISTER_ARGUMENT	0x9BC



/* PMC Scratch Registers */

#define AMD_PMC_SCRATCH_REG_CZN		0x94

#define AMD_PMC_SCRATCH_REG_YC		0xD14

#define AMD_PMC_SCRATCH_REG_1AH		0xF14



/* STB Registers */

#define AMD_PMC_STB_S2IDLE_PREPARE	0xC6000001

#define AMD_PMC_STB_S2IDLE_RESTORE	0xC6000002

#define AMD_PMC_STB_S2IDLE_CHECK	0xC6000003



/* Base address of SMU for mapping physical address to virtual address */

#define AMD_PMC_MAPPING_SIZE		0x01000

#define AMD_PMC_BASE_ADDR_OFFSET	0x10000

#define AMD_PMC_BASE_ADDR_LO		0x13B102E8

#define AMD_PMC_BASE_ADDR_HI		0x13B102EC

#define AMD_PMC_BASE_ADDR_LO_MASK	GENMASK(15, 0)

#define AMD_PMC_BASE_ADDR_HI_MASK	GENMASK(31, 20)



/* SMU Response Codes */

#define AMD_PMC_RESULT_OK                    0x01

#define AMD_PMC_RESULT_CMD_REJECT_BUSY       0xFC

#define AMD_PMC_RESULT_CMD_REJECT_PREREQ     0xFD

#define AMD_PMC_RESULT_CMD_UNKNOWN           0xFE

#define AMD_PMC_RESULT_FAILED                0xFF



/* FCH SSC Registers */

#define FCH_S0I3_ENTRY_TIME_L_OFFSET	0x30

#define FCH_S0I3_ENTRY_TIME_H_OFFSET	0x34

#define FCH_S0I3_EXIT_TIME_L_OFFSET	0x38

#define FCH_S0I3_EXIT_TIME_H_OFFSET	0x3C

#define FCH_SSC_MAPPING_SIZE		0x800

#define FCH_BASE_PHY_ADDR_LOW		0xFED81100

#define FCH_BASE_PHY_ADDR_HIGH		0x00000000



/* SMU Message Definations */

#define SMU_MSG_GETSMUVERSION		0x02

#define SMU_MSG_LOG_GETDRAM_ADDR_HI	0x04

#define SMU_MSG_LOG_GETDRAM_ADDR_LO	0x05

#define SMU_MSG_LOG_START		0x06

#define SMU_MSG_LOG_RESET		0x07

#define SMU_MSG_LOG_DUMP_DATA		0x08

#define SMU_MSG_GET_SUP_CONSTRAINTS	0x09



#define PMC_MSG_DELAY_MIN_US		50

#define RESPONSE_REGISTER_LOOP_MAX	20000



#define DELAY_MIN_US		2000

#define DELAY_MAX_US		3000



enum s2d_msg_port {

	MSG_PORT_PMC,

	MSG_PORT_S2D,
@@ -65,6 +118,34 @@ struct amd_pmc_dev { 
	struct stb_arg stb_arg;

};



struct amd_pmc_bit_map {

	const char *name;

	u32 bit_mask;

};



struct smu_metrics {

	u32 table_version;

	u32 hint_count;

	u32 s0i3_last_entry_status;

	u32 timein_s0i2;

	u64 timeentering_s0i3_lastcapture;

	u64 timeentering_s0i3_totaltime;

	u64 timeto_resume_to_os_lastcapture;

	u64 timeto_resume_to_os_totaltime;

	u64 timein_s0i3_lastcapture;

	u64 timein_s0i3_totaltime;

	u64 timein_swdrips_lastcapture;

	u64 timein_swdrips_totaltime;

	u64 timecondition_notmet_lastcapture[32];

	u64 timecondition_notmet_totaltime[32];

} __packed;



enum amd_pmc_def {

	MSG_TEST = 0x01,

	MSG_OS_HINT_PCO,

	MSG_OS_HINT_RN,

};



void amd_pmc_process_restore_quirks(struct amd_pmc_dev *dev);

void amd_pmc_quirks_init(struct amd_pmc_dev *dev);

void amd_mp2_stb_init(struct amd_pmc_dev *dev);