Commit e4c33fff authored by Daniel Miess's avatar Daniel Miess Committed by Alex Deucher
Browse files

drm/amd/display: Enable physymclk RCO 



[Why]
Enable the last of the RCO options for dcn35

[How]
Breakout RCO from dccg35_set_physymclk so that
physymclk RCO can be set in dccg_init without
disabling physymclk

Reviewed-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: default avatarJun Lei <jun.lei@amd.com>
Acked-by: default avatarHersen Wu <hersenxs.wu@amd.com>
Signed-off-by: default avatarDaniel Miess <daniel.miess@amd.com>
Signed-off-by: default avatarHersen Wu <hersenxs.wu@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 90f2f833

drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c

+40 −32
Original line number Diff line number Diff line
@@ -325,6 +325,43 @@ static void dccg35_set_dpstreamclk( 
	}

}



static void dccg35_set_physymclk_root_clock_gating(

		struct dccg *dccg,

		int phy_inst,

		bool enable)

{

	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);



	if (!dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

		return;



	switch (phy_inst) {

	case 0:

		REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

				PHYASYMCLK_ROOT_GATE_DISABLE, enable ? 1 : 0);

		break;

	case 1:

		REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

				PHYBSYMCLK_ROOT_GATE_DISABLE, enable ? 1 : 0);

		break;

	case 2:

		REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

				PHYCSYMCLK_ROOT_GATE_DISABLE, enable ? 1 : 0);

		break;

	case 3:

		REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

				PHYDSYMCLK_ROOT_GATE_DISABLE, enable ? 1 : 0);

		break;

	case 4:

		REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

				PHYESYMCLK_ROOT_GATE_DISABLE, enable ? 1 : 0);

		break;

	default:

		BREAK_TO_DEBUGGER();

		return;

	}

}



static void dccg35_set_physymclk(

		struct dccg *dccg,

		int phy_inst,
@@ -340,16 +377,10 @@ static void dccg35_set_physymclk( 
			REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL,

					PHYASYMCLK_EN, 1,

					PHYASYMCLK_SRC_SEL, clk_src);

			if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

				REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

					PHYASYMCLK_ROOT_GATE_DISABLE, 1);

		} else {

			REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL,

					PHYASYMCLK_EN, 0,

					PHYASYMCLK_SRC_SEL, 0);

			if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

				REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

					PHYASYMCLK_ROOT_GATE_DISABLE, 0);

		}

		break;

	case 1:
@@ -357,16 +388,10 @@ static void dccg35_set_physymclk( 
			REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL,

					PHYBSYMCLK_EN, 1,

					PHYBSYMCLK_SRC_SEL, clk_src);

			if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

				REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

					PHYBSYMCLK_ROOT_GATE_DISABLE, 1);

		} else {

			REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL,

					PHYBSYMCLK_EN, 0,

					PHYBSYMCLK_SRC_SEL, 0);

			if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

				REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

					PHYBSYMCLK_ROOT_GATE_DISABLE, 0);

		}

		break;

	case 2:
@@ -374,16 +399,10 @@ static void dccg35_set_physymclk( 
			REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL,

					PHYCSYMCLK_EN, 1,

					PHYCSYMCLK_SRC_SEL, clk_src);

			if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

				REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

					PHYCSYMCLK_ROOT_GATE_DISABLE, 1);

		} else {

			REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL,

					PHYCSYMCLK_EN, 0,

					PHYCSYMCLK_SRC_SEL, 0);

			if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

				REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

					PHYCSYMCLK_ROOT_GATE_DISABLE, 0);

		}

		break;

	case 3:
@@ -391,16 +410,10 @@ static void dccg35_set_physymclk( 
			REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL,

					PHYDSYMCLK_EN, 1,

					PHYDSYMCLK_SRC_SEL, clk_src);

			if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

				REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

					PHYDSYMCLK_ROOT_GATE_DISABLE, 1);

		} else {

			REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL,

					PHYDSYMCLK_EN, 0,

					PHYDSYMCLK_SRC_SEL, 0);

			if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

				REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

					PHYDSYMCLK_ROOT_GATE_DISABLE, 0);

		}

		break;

	case 4:
@@ -408,16 +421,10 @@ static void dccg35_set_physymclk( 
			REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL,

					PHYESYMCLK_EN, 1,

					PHYESYMCLK_SRC_SEL, clk_src);

			if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

				REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

					PHYESYMCLK_ROOT_GATE_DISABLE, 1);

		} else {

			REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL,

					PHYESYMCLK_EN, 0,

					PHYESYMCLK_SRC_SEL, 0);

			if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

				REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

					PHYESYMCLK_ROOT_GATE_DISABLE, 0);

		}

		break;

	default:
@@ -490,8 +497,8 @@ void dccg35_init(struct dccg *dccg) 


	if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

		for (otg_inst = 0; otg_inst < 5; otg_inst++)

			dccg35_set_physymclk(dccg, otg_inst,

					     PHYSYMCLK_FORCE_SRC_SYMCLK, false);

			dccg35_set_physymclk_root_clock_gating(dccg, otg_inst,

					false);

/*

	dccg35_enable_global_fgcg_rep(

		dccg, dccg->ctx->dc->debug.enable_fine_grain_clock_gating.bits
@@ -756,6 +763,7 @@ static const struct dccg_funcs dccg35_funcs = { 
	.disable_symclk32_le = dccg31_disable_symclk32_le,

	.set_symclk32_le_root_clock_gating = dccg31_set_symclk32_le_root_clock_gating,

	.set_physymclk = dccg35_set_physymclk,

	.set_physymclk_root_clock_gating = dccg35_set_physymclk_root_clock_gating,

	.set_dtbclk_dto = dccg35_set_dtbclk_dto,

	.set_audio_dtbclk_dto = dccg31_set_audio_dtbclk_dto,

	.set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,

drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c

+18 −2
Original line number Diff line number Diff line
@@ -610,7 +610,23 @@ static struct dce_hwseq_registers hwseq_reg; 
	HWS_SF(, DMU_CLK_CNTL, LONO_FGCG_REP_DIS, mask_sh),\

	HWS_SF(, DMU_CLK_CNTL, LONO_DISPCLK_GATE_DISABLE, mask_sh),\

	HWS_SF(, DMU_CLK_CNTL, LONO_SOCCLK_GATE_DISABLE, mask_sh),\

	HWS_SF(, DMU_CLK_CNTL, LONO_DMCUBCLK_GATE_DISABLE, mask_sh)

	HWS_SF(, DMU_CLK_CNTL, LONO_DMCUBCLK_GATE_DISABLE, mask_sh),\

	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_FE_GATE_DISABLE, mask_sh), \

	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_FE_GATE_DISABLE, mask_sh), \

	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_FE_GATE_DISABLE, mask_sh), \

	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_FE_GATE_DISABLE, mask_sh), \

	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_FE_GATE_DISABLE, mask_sh), \

	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, mask_sh), \

	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_GATE_DISABLE, mask_sh), \

	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_GATE_DISABLE, mask_sh), \

	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_GATE_DISABLE, mask_sh), \

	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_GATE_DISABLE, mask_sh), \

	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_GATE_DISABLE, mask_sh), \

	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, mask_sh), \

	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_ROOT_GATE_DISABLE, mask_sh), \

	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_ROOT_GATE_DISABLE, mask_sh), \

	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_ROOT_GATE_DISABLE, mask_sh), \

	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_ROOT_GATE_DISABLE, mask_sh)



static const struct dce_hwseq_shift hwseq_shift = {

		HWSEQ_DCN35_MASK_SH_LIST(__SHIFT)
@@ -725,7 +741,7 @@ static const struct dc_debug_options debug_defaults_drv = { 
			.symclk32_se = true,

			.symclk32_le = true,

			.symclk_fe = true,

			.physymclk = false, // Prevents eDP light up

			.physymclk = true,

			.dpiasymclk = true,

		}

	},

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

+17 −1
Original line number Diff line number Diff line
@@ -1183,7 +1183,23 @@ struct dce_hwseq_registers { 
	type LONO_FGCG_REP_DIS;\

	type LONO_DISPCLK_GATE_DISABLE;\

	type LONO_SOCCLK_GATE_DISABLE;\

	type LONO_DMCUBCLK_GATE_DISABLE;

	type LONO_DMCUBCLK_GATE_DISABLE;\

	type SYMCLKA_FE_GATE_DISABLE;\

	type SYMCLKB_FE_GATE_DISABLE;\

	type SYMCLKC_FE_GATE_DISABLE;\

	type SYMCLKD_FE_GATE_DISABLE;\

	type SYMCLKE_FE_GATE_DISABLE;\

	type HDMICHARCLK0_GATE_DISABLE;\

	type SYMCLKA_GATE_DISABLE;\

	type SYMCLKB_GATE_DISABLE;\

	type SYMCLKC_GATE_DISABLE;\

	type SYMCLKD_GATE_DISABLE;\

	type SYMCLKE_GATE_DISABLE;\

	type PHYASYMCLK_ROOT_GATE_DISABLE;\

	type PHYBSYMCLK_ROOT_GATE_DISABLE;\

	type PHYCSYMCLK_ROOT_GATE_DISABLE;\

	type PHYDSYMCLK_ROOT_GATE_DISABLE;\

	type PHYESYMCLK_ROOT_GATE_DISABLE;



struct dce_hwseq_shift {

	HWSEQ_REG_FIELD_LIST(uint8_t)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

+22 −2
Original line number Diff line number Diff line
@@ -146,7 +146,15 @@ void dcn35_init_hw(struct dc *dc) 
	}



	REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);

	REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0x3F000000);

	REG_WRITE(DCCG_GATE_DISABLE_CNTL2,  0);



	/* Disable gating for PHYASYMCLK. This will be enabled in dccg if needed */

	REG_UPDATE_5(DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, 1,

			PHYBSYMCLK_ROOT_GATE_DISABLE, 1,

			PHYCSYMCLK_ROOT_GATE_DISABLE, 1,

			PHYDSYMCLK_ROOT_GATE_DISABLE, 1,

			PHYESYMCLK_ROOT_GATE_DISABLE, 1);



	REG_WRITE(DCCG_GATE_DISABLE_CNTL5, 0x1f7c3fcf);



	// Initialize the dccg
@@ -275,7 +283,19 @@ void dcn35_init_hw(struct dc *dc) 
	if (!dc->debug.disable_clock_gate) {

		/* enable all DCN clock gating */

		REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);

		REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);



		REG_UPDATE_5(DCCG_GATE_DISABLE_CNTL2, SYMCLKA_FE_GATE_DISABLE, 0,

				SYMCLKB_FE_GATE_DISABLE, 0,

				SYMCLKC_FE_GATE_DISABLE, 0,

				SYMCLKD_FE_GATE_DISABLE, 0,

				SYMCLKE_FE_GATE_DISABLE, 0);

		REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, 0);

		REG_UPDATE_5(DCCG_GATE_DISABLE_CNTL2, SYMCLKA_GATE_DISABLE, 0,

				SYMCLKB_GATE_DISABLE, 0,

				SYMCLKC_GATE_DISABLE, 0,

				SYMCLKD_GATE_DISABLE, 0,

				SYMCLKE_GATE_DISABLE, 0);



		REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);

	}

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

+5 −0
Original line number Diff line number Diff line
@@ -141,6 +141,11 @@ struct dccg_funcs { 
			enum physymclk_clock_source clk_src,

			bool force_enable);



	void (*set_physymclk_root_clock_gating)(

			struct dccg *dccg,

			int phy_inst,

			bool enable);



	void (*set_dtbclk_dto)(

			struct dccg *dccg,

			const struct dtbclk_dto_params *params);