Commit e5075d8e authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'riscv-for-linus-6.8-mw4' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux 

Pull more RISC-V updates from Palmer Dabbelt:

 - Support for tuning for systems with fast misaligned accesses.

 - Support for SBI-based suspend.

 - Support for the new SBI debug console extension.

 - The T-Head CMOs now use PA-based flushes.

 - Support for enabling the V extension in kernel code.

 - Optimized IP checksum routines.

 - Various ftrace improvements.

 - Support for archrandom, which depends on the Zkr extension.

 - The build is no longer broken under NET=n, KUNIT=y for ports that
   don't define their own ipv6 checksum.

* tag 'riscv-for-linus-6.8-mw4' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (56 commits)
  lib: checksum: Fix build with CONFIG_NET=n
  riscv: lib: Check if output in asm goto supported
  riscv: Fix build error on rv32 + XIP
  riscv: optimize ELF relocation function in riscv
  RISC-V: Implement archrandom when Zkr is available
  riscv: Optimize hweight API with Zbb extension
  riscv: add dependency among Image(.gz), loader(.bin), and vmlinuz.efi
  samples: ftrace: Add RISC-V support for SAMPLE_FTRACE_DIRECT[_MULTI]
  riscv: ftrace: Add DYNAMIC_FTRACE_WITH_DIRECT_CALLS support
  riscv: ftrace: Make function graph use ftrace directly
  riscv: select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY
  lib/Kconfig.debug: Update AS_HAS_NON_CONST_LEB128 comment and name
  riscv: Restrict DWARF5 when building with LLVM to known working versions
  riscv: Hoist linker relaxation disabling logic into Kconfig
  kunit: Add tests for csum_ipv6_magic and ip_fast_csum
  riscv: Add checksum library
  riscv: Add checksum header
  riscv: Add static key for misaligned accesses
  asm-generic: Improve csum_fold
  RISC-V: selftests: cbo: Ensure asm operands match constraints
  ...
parents c25b24fa f24a7010

Documentation/devicetree/bindings/riscv/cpus.yaml

+7 −2
Original line number Diff line number Diff line
@@ -63,8 +63,8 @@ properties: 


  mmu-type:

    description:

      Identifies the MMU address translation mode used on this

      hart.  These values originate from the RISC-V Privileged

      Identifies the largest MMU address translation mode supported by

      this hart.  These values originate from the RISC-V Privileged

      Specification document, available from

      https://riscv.org/specifications/

    $ref: /schemas/types.yaml#/definitions/string
@@ -80,6 +80,11 @@ properties: 
    description:

      The blocksize in bytes for the Zicbom cache operations.



  riscv,cbop-block-size:

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      The blocksize in bytes for the Zicbop cache operations.



  riscv,cboz-block-size:

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

Documentation/devicetree/bindings/riscv/extensions.yaml

+1 −1
Original line number Diff line number Diff line
@@ -48,7 +48,7 @@ properties: 
      insensitive, letters in the riscv,isa string must be all

      lowercase.

    $ref: /schemas/types.yaml#/definitions/string

    pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$

    pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[0-9a-z])+)?(?:_[hsxz](?:[0-9a-z])+)*$

    deprecated: true



  riscv,isa-base:

Documentation/features/vm/TLB/arch-support.txt

+1 −1
Original line number Diff line number Diff line
@@ -20,7 +20,7 @@ 
    |    openrisc: |  ..  |

    |      parisc: | TODO |

    |     powerpc: | TODO |

    |       riscv: | TODO |

    |       riscv: |  ok  |

    |        s390: | TODO |

    |          sh: | TODO |

    |       sparc: | TODO |

arch/riscv/Kconfig

+56 −1
Original line number Diff line number Diff line
@@ -53,6 +53,7 @@ config RISCV 
	select ARCH_USE_MEMTEST

	select ARCH_USE_QUEUED_RWLOCKS

	select ARCH_USES_CFI_TRAPS if CFI_CLANG

	select ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH if SMP && MMU

	select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU

	select ARCH_WANT_FRAME_POINTERS

	select ARCH_WANT_GENERAL_HUGETLB if !RISCV_ISA_SVNAPOT
@@ -66,9 +67,10 @@ config RISCV 
	select CLINT_TIMER if !MMU

	select CLONE_BACKWARDS

	select COMMON_CLK

	select CPU_PM if CPU_IDLE || HIBERNATION

	select CPU_PM if CPU_IDLE || HIBERNATION || SUSPEND

	select EDAC_SUPPORT

	select FRAME_POINTER if PERF_EVENTS || (FUNCTION_TRACER && !DYNAMIC_FTRACE)

	select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY if DYNAMIC_FTRACE

	select GENERIC_ARCH_TOPOLOGY

	select GENERIC_ATOMIC64 if !64BIT

	select GENERIC_CLOCKEVENTS_BROADCAST if SMP
@@ -115,6 +117,7 @@ config RISCV 
	select HAVE_DEBUG_KMEMLEAK

	select HAVE_DMA_CONTIGUOUS if MMU

	select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && MMU && (CLANG_SUPPORTS_DYNAMIC_FTRACE || GCC_SUPPORTS_DYNAMIC_FTRACE)

	select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS

	select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE

	select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL

	select HAVE_FUNCTION_GRAPH_TRACER
@@ -142,6 +145,8 @@ config RISCV 
	select HAVE_REGS_AND_STACK_ACCESS_API

	select HAVE_RETHOOK if !XIP_KERNEL

	select HAVE_RSEQ

	select HAVE_SAMPLE_FTRACE_DIRECT

	select HAVE_SAMPLE_FTRACE_DIRECT_MULTI

	select HAVE_STACKPROTECTOR

	select HAVE_SYSCALL_TRACEPOINTS

	select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU
@@ -183,6 +188,20 @@ config HAVE_SHADOW_CALL_STACK 
	# https://github.com/riscv-non-isa/riscv-elf-psabi-doc/commit/a484e843e6eeb51f0cb7b8819e50da6d2444d769

	depends on $(ld-option,--no-relax-gp)



config RISCV_USE_LINKER_RELAXATION

	def_bool y

	# https://github.com/llvm/llvm-project/commit/6611d58f5bbcbec77262d392e2923e1d680f6985

	depends on !LD_IS_LLD || LLD_VERSION >= 150000



# https://github.com/llvm/llvm-project/commit/bbc0f99f3bc96f1db16f649fc21dd18e5b0918f6

config ARCH_HAS_BROKEN_DWARF5

	def_bool y

	depends on RISCV_USE_LINKER_RELAXATION

	# https://github.com/llvm/llvm-project/commit/1df5ea29b43690b6622db2cad7b745607ca4de6a

	depends on AS_IS_LLVM && AS_VERSION < 180000

	# https://github.com/llvm/llvm-project/commit/7ffabb61a5569444b5ac9322e22e5471cc5e4a77

	depends on LD_IS_LLD && LLD_VERSION < 180000



config ARCH_MMAP_RND_BITS_MIN

	default 18 if 64BIT

	default 8
@@ -529,6 +548,28 @@ config RISCV_ISA_V_DEFAULT_ENABLE 


	  If you don't know what to do here, say Y.



config RISCV_ISA_V_UCOPY_THRESHOLD

	int "Threshold size for vectorized user copies"

	depends on RISCV_ISA_V

	default 768

	help

	  Prefer using vectorized copy_to_user()/copy_from_user() when the

	  workload size exceeds this value.



config RISCV_ISA_V_PREEMPTIVE

	bool "Run kernel-mode Vector with kernel preemption"

	depends on PREEMPTION

	depends on RISCV_ISA_V

	default y

	help

	  Usually, in-kernel SIMD routines are run with preemption disabled.

	  Functions which envoke long running SIMD thus must yield core's

	  vector unit to prevent blocking other tasks for too long.



	  This config allows kernel to run SIMD without explicitly disable

	  preemption. Enabling this config will result in higher memory

	  consumption due to the allocation of per-task's kernel Vector context.



config TOOLCHAIN_HAS_ZBB

	bool

	default y
@@ -655,6 +696,20 @@ config RISCV_MISALIGNED 
	  load/store for both kernel and userspace. When disable, misaligned

	  accesses will generate SIGBUS in userspace and panic in kernel.



config RISCV_EFFICIENT_UNALIGNED_ACCESS

	bool "Assume the CPU supports fast unaligned memory accesses"

	depends on NONPORTABLE

	select DCACHE_WORD_ACCESS if MMU

	select HAVE_EFFICIENT_UNALIGNED_ACCESS

	help

	  Say Y here if you want the kernel to assume that the CPU supports

	  efficient unaligned memory accesses.  When enabled, this option

	  improves the performance of the kernel on such CPUs.  However, the

	  kernel will run much more slowly, or will not be able to run at all,

	  on CPUs that do not support efficient unaligned memory accesses.



	  If unsure what to do here, say N.



endmenu # "Platform type"



menu "Kernel features"

arch/riscv/Kconfig.errata

+1 −0
Original line number Diff line number Diff line
@@ -98,6 +98,7 @@ config ERRATA_THEAD_CMO 
	depends on ERRATA_THEAD && MMU

	select DMA_DIRECT_REMAP

	select RISCV_DMA_NONCOHERENT

	select RISCV_NONSTANDARD_CACHE_OPS

	default y

	help

	  This will apply the cache management errata to handle the