Commit e629bf40 authored by AngeloGioacchino Del Regno's avatar AngeloGioacchino Del Regno Committed by Chen-Yu Tsai
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dt-bindings: clock: mediatek: Add clock driver bindings for MT6795 



Add the bindings for the clock drivers of the MediaTek Helio X10
MT6795 SoC.

Signed-off-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220921091455.41327-5-angelogioacchino.delregno@collabora.com


Signed-off-by: default avatarChen-Yu Tsai <wenst@chromium.org>
parent f098c088

Documentation/devicetree/bindings/clock/mediatek,mt6795-clock.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/mediatek,mt6795-clock.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: MediaTek Functional Clock Controller for MT6795



maintainers:

  - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

  - Chun-Jie Chen <chun-jie.chen@mediatek.com>



description: |

  The clock architecture in MediaTek like below

  PLLs -->

          dividers -->

                      muxes

                           -->

                              clock gate



  The devices provide clock gate control in different IP blocks.



properties:

  compatible:

    enum:

      - mediatek,mt6795-mfgcfg

      - mediatek,mt6795-vdecsys

      - mediatek,mt6795-vencsys



  reg:

    maxItems: 1



  '#clock-cells':

    const: 1



required:

  - compatible

  - reg

  - '#clock-cells'



additionalProperties: false



examples:

  - |

    soc {

        #address-cells = <2>;

        #size-cells = <2>;



        mfgcfg: clock-controller@13000000 {

            compatible = "mediatek,mt6795-mfgcfg";

            reg = <0 0x13000000 0 0x1000>;

            #clock-cells = <1>;

        };



        vdecsys: clock-controller@16000000 {

            compatible = "mediatek,mt6795-vdecsys";

            reg = <0 0x16000000 0 0x1000>;

            #clock-cells = <1>;

        };



        vencsys: clock-controller@18000000 {

            compatible = "mediatek,mt6795-vencsys";

            reg = <0 0x18000000 0 0x1000>;

            #clock-cells = <1>;

        };

    };

Documentation/devicetree/bindings/clock/mediatek,mt6795-sys-clock.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/mediatek,mt6795-sys-clock.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: MediaTek System Clock Controller for MT6795



maintainers:

  - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

  - Chun-Jie Chen <chun-jie.chen@mediatek.com>



description:

  The Mediatek system clock controller provides various clocks and system

  configuration like reset and bus protection on MT6795.



properties:

  compatible:

    items:

      - enum:

          - mediatek,mt6795-apmixedsys

          - mediatek,mt6795-infracfg

          - mediatek,mt6795-pericfg

          - mediatek,mt6795-topckgen

      - const: syscon



  reg:

    maxItems: 1



  '#clock-cells':

    const: 1



  '#reset-cells':

    const: 1



required:

  - compatible

  - reg

  - '#clock-cells'



additionalProperties: false



examples:

  - |

    soc {

        #address-cells = <2>;

        #size-cells = <2>;



        topckgen: clock-controller@10000000 {

            compatible = "mediatek,mt6795-topckgen", "syscon";

            reg = <0 0x10000000 0 0x1000>;

            #clock-cells = <1>;

        };

    };