Commit e677fab8 authored by Quan Zhou's avatar Quan Zhou Committed by Anup Patel
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KVM: riscv: selftests: Add Zicbop extension to get-reg-list test 



The KVM RISC-V allows Zicbop extension for Guest/VM
so add them to get-reg-list test.

Signed-off-by: default avatarQuan Zhou <zhouquan@iscas.ac.cn>
Reviewed-by: default avatarAndrew Jones <ajones@ventanamicro.com>
Reviewed-by: default avatarNutty Liu <nutty.liu@hotmail.com>
Link: https://lore.kernel.org/r/076908690c15070f907f43d2ff81ba7e95582ec7.1754646071.git.zhouquan@iscas.ac.cn


Signed-off-by: default avatarAnup Patel <anup@brainfault.org>
parent 44c3d084

tools/testing/selftests/kvm/riscv/get-reg-list.c

+16 −0
Original line number Diff line number Diff line
@@ -83,6 +83,7 @@ bool filter_reg(__u64 reg) 
	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFH:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFHMIN:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOM:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOP:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOZ:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICCRSE:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICNTR:
@@ -255,6 +256,8 @@ static const char *config_id_to_str(const char *prefix, __u64 id) 
		return "KVM_REG_RISCV_CONFIG_REG(zicbom_block_size)";

	case KVM_REG_RISCV_CONFIG_REG(zicboz_block_size):

		return "KVM_REG_RISCV_CONFIG_REG(zicboz_block_size)";

	case KVM_REG_RISCV_CONFIG_REG(zicbop_block_size):

		return "KVM_REG_RISCV_CONFIG_REG(zicbop_block_size)";

	case KVM_REG_RISCV_CONFIG_REG(mvendorid):

		return "KVM_REG_RISCV_CONFIG_REG(mvendorid)";

	case KVM_REG_RISCV_CONFIG_REG(marchid):
@@ -535,6 +538,7 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off) 
		KVM_ISA_EXT_ARR(ZFH),

		KVM_ISA_EXT_ARR(ZFHMIN),

		KVM_ISA_EXT_ARR(ZICBOM),

		KVM_ISA_EXT_ARR(ZICBOP),

		KVM_ISA_EXT_ARR(ZICBOZ),

		KVM_ISA_EXT_ARR(ZICCRSE),

		KVM_ISA_EXT_ARR(ZICNTR),
@@ -780,10 +784,13 @@ void print_reg(const char *prefix, __u64 id) 
 */

static __u64 base_regs[] = {

	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(isa),

	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicbom_block_size),

	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(mvendorid),

	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(marchid),

	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(mimpid),

	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicboz_block_size),

	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(satp_mode),

	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicbop_block_size),

	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.pc),

	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.ra),

	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.sp),
@@ -864,6 +871,11 @@ static __u64 zicbom_regs[] = { 
	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOM,

};



static __u64 zicbop_regs[] = {

	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicbop_block_size),

	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOP,

};



static __u64 zicboz_regs[] = {

	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicboz_block_size),

	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOZ,
@@ -1012,6 +1024,8 @@ static __u64 vector_regs[] = { 
	 .regs = sbi_sta_regs, .regs_n = ARRAY_SIZE(sbi_sta_regs),}

#define SUBLIST_ZICBOM \

	{"zicbom", .feature = KVM_RISCV_ISA_EXT_ZICBOM, .regs = zicbom_regs, .regs_n = ARRAY_SIZE(zicbom_regs),}

#define SUBLIST_ZICBOP \

	{"zicbop", .feature = KVM_RISCV_ISA_EXT_ZICBOP, .regs = zicbop_regs, .regs_n = ARRAY_SIZE(zicbop_regs),}

#define SUBLIST_ZICBOZ \

	{"zicboz", .feature = KVM_RISCV_ISA_EXT_ZICBOZ, .regs = zicboz_regs, .regs_n = ARRAY_SIZE(zicboz_regs),}

#define SUBLIST_AIA \
@@ -1130,6 +1144,7 @@ KVM_ISA_EXT_SIMPLE_CONFIG(zfa, ZFA); 
KVM_ISA_EXT_SIMPLE_CONFIG(zfh, ZFH);

KVM_ISA_EXT_SIMPLE_CONFIG(zfhmin, ZFHMIN);

KVM_ISA_EXT_SUBLIST_CONFIG(zicbom, ZICBOM);

KVM_ISA_EXT_SUBLIST_CONFIG(zicbop, ZICBOP);

KVM_ISA_EXT_SUBLIST_CONFIG(zicboz, ZICBOZ);

KVM_ISA_EXT_SIMPLE_CONFIG(ziccrse, ZICCRSE);

KVM_ISA_EXT_SIMPLE_CONFIG(zicntr, ZICNTR);
@@ -1204,6 +1219,7 @@ struct vcpu_reg_list *vcpu_configs[] = { 
	&config_zfh,

	&config_zfhmin,

	&config_zicbom,

	&config_zicbop,

	&config_zicboz,

	&config_ziccrse,

	&config_zicntr,