Commit e71e0012 authored by Jason Gunthorpe's avatar Jason Gunthorpe Committed by Joerg Roedel
Browse files

iommupt: Add the RISC-V page table format 



The RISC-V format is a fairly simple 5 level page table not unlike the x86
one. It has optional support for a single contiguous page size of 64k (16
x 4k).

The specification describes a 32-bit format, the general code can support
it via a #define but the iommu side implementation has been left off until
a user comes.

Tested-by: default avatarVincent Chen <vincent.chen@sifive.com>
Acked-by: Paul Walmsley <pjw@kernel.org> # arch/riscv
Reviewed-by: default avatarTomasz Jeznach <tjeznach@rivosinc.com>
Tested-by: default avatarTomasz Jeznach <tjeznach@rivosinc.com>
Signed-off-by: default avatarJason Gunthorpe <jgg@nvidia.com>
Signed-off-by: default avatarJoerg Roedel <joerg.roedel@amd.com>
parent f338e773

drivers/iommu/generic_pt/.kunitconfig

+1 −0
Original line number Diff line number Diff line
@@ -5,6 +5,7 @@ CONFIG_DEBUG_GENERIC_PT=y 
CONFIG_IOMMU_PT=y

CONFIG_IOMMU_PT_AMDV1=y

CONFIG_IOMMU_PT_VTDSS=y

CONFIG_IOMMU_PT_RISCV64=y

CONFIG_IOMMU_PT_X86_64=y

CONFIG_IOMMU_PT_KUNIT_TEST=y

drivers/iommu/generic_pt/Kconfig

+11 −0
Original line number Diff line number Diff line
@@ -52,6 +52,16 @@ config IOMMU_PT_VTDSS 


	  Selected automatically by an IOMMU driver that uses this format.



config IOMMU_PT_RISCV64

       tristate "IOMMU page table for RISC-V 64 bit Sv57/Sv48/Sv39"

	depends on !GENERIC_ATOMIC64 # for cmpxchg64

	help

	  iommu_domain implementation for RISC-V 64 bit 3/4/5 level page table.

	  It supports 4K/2M/1G/512G/256T page sizes and can decode a sign

	  extended portion of the 64 bit IOVA space.



	  Selected automatically by an IOMMU driver that uses this format.



config IOMMU_PT_X86_64

	tristate "IOMMU page table for x86 64-bit, 4/5 levels"

	depends on !GENERIC_ATOMIC64 # for cmpxchg64
@@ -66,6 +76,7 @@ config IOMMU_PT_KUNIT_TEST 
	tristate "IOMMU Page Table KUnit Test" if !KUNIT_ALL_TESTS

	depends on KUNIT

	depends on IOMMU_PT_AMDV1 || !IOMMU_PT_AMDV1

	depends on IOMMU_PT_RISCV64 || !IOMMU_PT_RISCV64

	depends on IOMMU_PT_X86_64 || !IOMMU_PT_X86_64

	depends on IOMMU_PT_VTDSS || !IOMMU_PT_VTDSS

	default KUNIT_ALL_TESTS

drivers/iommu/generic_pt/fmt/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -5,6 +5,8 @@ iommu_pt_fmt-$(CONFIG_IOMMUFD_TEST) += mock 


iommu_pt_fmt-$(CONFIG_IOMMU_PT_VTDSS) += vtdss



iommu_pt_fmt-$(CONFIG_IOMMU_PT_RISCV64) += riscv64



iommu_pt_fmt-$(CONFIG_IOMMU_PT_X86_64) += x86_64



IOMMU_PT_KUNIT_TEST :=

drivers/iommu/generic_pt/fmt/defs_riscv.h

0 → 100644
+29 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2025, NVIDIA CORPORATION & AFFILIATES

 *

 */

#ifndef __GENERIC_PT_FMT_DEFS_RISCV_H

#define __GENERIC_PT_FMT_DEFS_RISCV_H



#include <linux/generic_pt/common.h>

#include <linux/types.h>



#ifdef PT_RISCV_32BIT

typedef u32 pt_riscv_entry_t;

#define riscvpt_write_attrs riscv32pt_write_attrs

#else

typedef u64 pt_riscv_entry_t;

#define riscvpt_write_attrs riscv64pt_write_attrs

#endif



typedef pt_riscv_entry_t pt_vaddr_t;

typedef u64 pt_oaddr_t;



struct riscvpt_write_attrs {

	pt_riscv_entry_t descriptor_bits;

	gfp_t gfp;

};

#define pt_write_attrs riscvpt_write_attrs



#endif

drivers/iommu/generic_pt/fmt/iommu_riscv64.c

0 → 100644
+11 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2025, NVIDIA CORPORATION & AFFILIATES

 */

#define PT_FMT riscv

#define PT_FMT_VARIANT 64

#define PT_SUPPORTED_FEATURES                                  \

	(BIT(PT_FEAT_SIGN_EXTEND) | BIT(PT_FEAT_FLUSH_RANGE) | \

	 BIT(PT_FEAT_RISCV_SVNAPOT_64K))



#include "iommu_template.h"