Commit e7e80b66 authored by Sean Christopherson's avatar Sean Christopherson
Browse files

x86/cpu: KVM: Add common defines for architectural memory types (PAT, MTRRs, etc.) 



Add defines for the architectural memory types that can be shoved into
various MSRs and registers, e.g. MTRRs, PAT, VMX capabilities MSRs, EPTPs,
etc.  While most MSRs/registers support only a subset of all memory types,
the values themselves are architectural and identical across all users.

Leave the goofy MTRR_TYPE_* definitions as-is since they are in a uapi
header, but add compile-time assertions to connect the dots (and sanity
check that the msr-index.h values didn't get fat-fingered).

Keep the VMX_EPTP_MT_* defines so that it's slightly more obvious that the
EPTP holds a single memory type in 3 of its 64 bits; those bits just
happen to be 2:0, i.e. don't need to be shifted.

Opportunistically use X86_MEMTYPE_WB instead of an open coded '6' in
setup_vmcs_config().

No functional change intended.

Reviewed-by: default avatarThomas Gleixner <tglx@linutronix.de>
Acked-by: default avatarKai Huang <kai.huang@intel.com>
Reviewed-by: default avatarXiaoyao Li <xiaoyao.li@intel.com>
Reviewed-by: default avatarKai Huang <kai.huang@intel.com>
Link: https://lore.kernel.org/r/20240605231918.2915961-2-seanjc@google.com


Signed-off-by: default avatarSean Christopherson <seanjc@google.com>
parent 47ac09b9

arch/x86/include/asm/msr-index.h

+14 −1
Original line number Diff line number Diff line
@@ -36,6 +36,20 @@ 
#define EFER_FFXSR		(1<<_EFER_FFXSR)

#define EFER_AUTOIBRS		(1<<_EFER_AUTOIBRS)



/*

 * Architectural memory types that are common to MTRRs, PAT, VMX MSRs, etc.

 * Most MSRs support/allow only a subset of memory types, but the values

 * themselves are common across all relevant MSRs.

 */

#define X86_MEMTYPE_UC		0ull	/* Uncacheable, a.k.a. Strong Uncacheable */

#define X86_MEMTYPE_WC		1ull	/* Write Combining */

/* RESERVED			2 */

/* RESERVED			3 */

#define X86_MEMTYPE_WT		4ull	/* Write Through */

#define X86_MEMTYPE_WP		5ull	/* Write Protected */

#define X86_MEMTYPE_WB		6ull	/* Write Back */

#define X86_MEMTYPE_UC_MINUS	7ull	/* Weak Uncacheabled (PAT only) */



/* FRED MSRs */

#define MSR_IA32_FRED_RSP0	0x1cc			/* Level 0 stack pointer */

#define MSR_IA32_FRED_RSP1	0x1cd			/* Level 1 stack pointer */
@@ -1163,7 +1177,6 @@ 
#define VMX_BASIC_64		0x0001000000000000LLU

#define VMX_BASIC_MEM_TYPE_SHIFT	50

#define VMX_BASIC_MEM_TYPE_MASK	0x003c000000000000LLU

#define VMX_BASIC_MEM_TYPE_WB	6LLU

#define VMX_BASIC_INOUT		0x0040000000000000LLU



/* Resctrl MSRs: */

arch/x86/include/asm/vmx.h

+3 −2
Original line number Diff line number Diff line
@@ -508,9 +508,10 @@ enum vmcs_field { 
#define VMX_EPTP_PWL_4				0x18ull

#define VMX_EPTP_PWL_5				0x20ull

#define VMX_EPTP_AD_ENABLE_BIT			(1ull << 6)

/* The EPTP memtype is encoded in bits 2:0, i.e. doesn't need to be shifted. */

#define VMX_EPTP_MT_MASK			0x7ull

#define VMX_EPTP_MT_WB				0x6ull

#define VMX_EPTP_MT_UC				0x0ull

#define VMX_EPTP_MT_WB				X86_MEMTYPE_WB

#define VMX_EPTP_MT_UC				X86_MEMTYPE_UC

#define VMX_EPT_READABLE_MASK			0x1ull

#define VMX_EPT_WRITABLE_MASK			0x2ull

#define VMX_EPT_EXECUTABLE_MASK			0x4ull

arch/x86/kernel/cpu/mtrr/mtrr.c

+6 −0
Original line number Diff line number Diff line
@@ -55,6 +55,12 @@ 


#include "mtrr.h"



static_assert(X86_MEMTYPE_UC == MTRR_TYPE_UNCACHABLE);

static_assert(X86_MEMTYPE_WC == MTRR_TYPE_WRCOMB);

static_assert(X86_MEMTYPE_WT == MTRR_TYPE_WRTHROUGH);

static_assert(X86_MEMTYPE_WP == MTRR_TYPE_WRPROT);

static_assert(X86_MEMTYPE_WB == MTRR_TYPE_WRBACK);



/* arch_phys_wc_add returns an MTRR register index plus this offset. */

#define MTRR_TO_PHYS_WC_OFFSET 1000

arch/x86/kvm/vmx/nested.c

+1 −1
Original line number Diff line number Diff line
@@ -7070,7 +7070,7 @@ static void nested_vmx_setup_basic(struct nested_vmx_msrs *msrs) 
		VMCS12_REVISION |

		VMX_BASIC_TRUE_CTLS |

		((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |

		(VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);

		(X86_MEMTYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);



	if (cpu_has_vmx_basic_inout())

		msrs->basic |= VMX_BASIC_INOUT;

arch/x86/kvm/vmx/vmx.c

+1 −1
Original line number Diff line number Diff line
@@ -2747,7 +2747,7 @@ static int setup_vmcs_config(struct vmcs_config *vmcs_conf, 
#endif



	/* Require Write-Back (WB) memory type for VMCS accesses. */

	if (((vmx_msr_high >> 18) & 15) != 6)

	if (((vmx_msr_high >> 18) & 15) != X86_MEMTYPE_WB)

		return -EIO;



	rdmsrl(MSR_IA32_VMX_MISC, misc_msr);