Commit e995fcde authored by Lu Baolu's avatar Lu Baolu Committed by Will Deacon
Browse files

iommu/vt-d: Remove control over Execute-Requested requests 



The VT-d specification has removed architectural support of the requests
with pasid with a value of 1 for Execute-Requested (ER). And the NXE bit
in the pasid table entry and XD bit in the first-stage paging Entries are
deprecated accordingly.

Remove the programming of these bits to make it consistent with the spec.

Suggested-by: default avatarJacob Pan <jacob.jun.pan@linux.intel.com>
Signed-off-by: default avatarLu Baolu <baolu.lu@linux.intel.com>
Reviewed-by: default avatarKevin Tian <kevin.tian@intel.com>
Link: https://lore.kernel.org/r/20240624032351.249858-1-baolu.lu@linux.intel.com
Link: https://lore.kernel.org/r/20240702130839.108139-4-baolu.lu@linux.intel.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 5fbf9737

drivers/iommu/intel/iommu.c

+2 −2
Original line number Diff line number Diff line
@@ -854,7 +854,7 @@ static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain, 
			domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE);

			pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;

			if (domain->use_first_level)

				pteval |= DMA_FL_PTE_XD | DMA_FL_PTE_US | DMA_FL_PTE_ACCESS;

				pteval |= DMA_FL_PTE_US | DMA_FL_PTE_ACCESS;



			tmp = 0ULL;

			if (!try_cmpxchg64(&pte->val, &tmp, pteval))
@@ -1872,7 +1872,7 @@ __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn, 
	attr = prot & (DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP);

	attr |= DMA_FL_PTE_PRESENT;

	if (domain->use_first_level) {

		attr |= DMA_FL_PTE_XD | DMA_FL_PTE_US | DMA_FL_PTE_ACCESS;

		attr |= DMA_FL_PTE_US | DMA_FL_PTE_ACCESS;

		if (prot & DMA_PTE_WRITE)

			attr |= DMA_FL_PTE_DIRTY;

	}

drivers/iommu/intel/iommu.h

+2 −4
Original line number Diff line number Diff line
@@ -49,7 +49,6 @@ 
#define DMA_FL_PTE_US		BIT_ULL(2)

#define DMA_FL_PTE_ACCESS	BIT_ULL(5)

#define DMA_FL_PTE_DIRTY	BIT_ULL(6)

#define DMA_FL_PTE_XD		BIT_ULL(63)



#define DMA_SL_PTE_DIRTY_BIT	9

#define DMA_SL_PTE_DIRTY	BIT_ULL(DMA_SL_PTE_DIRTY_BIT)
@@ -831,11 +830,10 @@ static inline void dma_clear_pte(struct dma_pte *pte) 
static inline u64 dma_pte_addr(struct dma_pte *pte)

{

#ifdef CONFIG_64BIT

	return pte->val & VTD_PAGE_MASK & (~DMA_FL_PTE_XD);

	return pte->val & VTD_PAGE_MASK;

#else

	/* Must have a full atomic 64-bit read */

	return  __cmpxchg64(&pte->val, 0ULL, 0ULL) &

			VTD_PAGE_MASK & (~DMA_FL_PTE_XD);

	return  __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK;

#endif

}

drivers/iommu/intel/pasid.c

+0 −1
Original line number Diff line number Diff line
@@ -336,7 +336,6 @@ int intel_pasid_setup_first_level(struct intel_iommu *iommu, 
	pasid_set_domain_id(pte, did);

	pasid_set_address_width(pte, iommu->agaw);

	pasid_set_page_snoop(pte, !!ecap_smpwc(iommu->ecap));

	pasid_set_nxe(pte);



	/* Setup Present and PASID Granular Transfer Type: */

	pasid_set_translation_type(pte, PASID_ENTRY_PGTT_FL_ONLY);

drivers/iommu/intel/pasid.h

+0 −10
Original line number Diff line number Diff line
@@ -247,16 +247,6 @@ static inline void pasid_set_page_snoop(struct pasid_entry *pe, bool value) 
	pasid_set_bits(&pe->val[1], 1 << 23, value << 23);

}



/*

 * Setup No Execute Enable bit (Bit 133) of a scalable mode PASID

 * entry. It is required when XD bit of the first level page table

 * entry is about to be set.

 */

static inline void pasid_set_nxe(struct pasid_entry *pe)

{

	pasid_set_bits(&pe->val[2], 1 << 5, 1 << 5);

}



/*

 * Setup the Page Snoop (PGSNP) field (Bit 88) of a scalable mode

 * PASID entry.