Commit e9e4b3a0 authored by Sung Joon Kim's avatar Sung Joon Kim Committed by Alex Deucher
Browse files

drm/amd/display: Enable Z10 flag for IPS FSM 



[why]
IPS FSM requires Z10 flag to be enabled to do save and restore the
registers properly.

[how]
Enable Z10 and use the correct function to determine Z10 capability

Reviewed-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: default avatarRodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: default avatarSung Joon Kim <sungjoon.kim@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 0a571e86

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

+2 −2
Original line number Diff line number Diff line
@@ -758,7 +758,7 @@ static const struct dc_debug_options debug_defaults_drv = { 
	//must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions

	.enable_double_buffered_dsc_pg_support = true,

	.enable_dp_dig_pixel_rate_div_policy = 1,

	.disable_z10 = true,

	.disable_z10 = false,

	.ignore_pg = true,

	.psp_disabled_wa = true,

	.ips2_eval_delay_us = 2000,
@@ -1722,7 +1722,7 @@ static bool dcn351_validate_bandwidth(struct dc *dc, 
		return out;



	DC_FP_START();

	dcn351_decide_zstate_support(dc, context);

	dcn35_decide_zstate_support(dc, context);

	DC_FP_END();



	return out;