Commit ea470fe3 authored by Tejas Bhumkar's avatar Tejas Bhumkar Committed by Michal Simek
Browse files

arm64: zynqmp: Disable Tri-state for MIO38 Pin 



gpio38 is used in SOM's kv260 to reset the Ethernet PHY.
At present, HW reset is not working properly as Tri-state 
is enabled for MIO38, causing inappropriate PHY register reads.

Disabled Tri-state for MIO38 to make HW reset work.

Tri-state disable :
ZynqMP> md 0xFF180208 2
ff180208: 00bfe7a3 00000540

Tri-state enable :
ZynqMP> md 0xFF180208 2
ff180208: 00bfe7e3 00000540

Signed-off-by: default avatarTejas Bhumkar <tejas.arvind.bhumkar@amd.com>
Link: https://lore.kernel.org/r/9f8a0687be407a8ffad610087074e94ebc4f5982.1704728353.git.michal.simek@amd.com
Signed-off-by: default avatarMichal Simek <michal.simek@amd.com>
parent 24e85ff0

arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso

+25 −0
Original line number Diff line number Diff line
@@ -169,6 +169,25 @@ phy0: ethernet-phy@1 { 
&pinctrl0 {

	status = "okay";



	pinctrl_gpio0_default: gpio0-default {

                conf {

                        groups = "gpio0_38_grp";

                        bias-pull-up;

                        power-source = <IO_STANDARD_LVCMOS18>;

                };



                mux {

                        groups = "gpio0_38_grp";

                        function = "gpio0";

                };



                conf-tx {

                        pins = "MIO38";

                        bias-disable;

                        output-enable;

                };

        };



	pinctrl_uart1_default: uart1-default {

		conf {

			groups = "uart1_9_grp";
@@ -324,6 +343,12 @@ mux { 
	};

};



&gpio {

        status = "okay";

        pinctrl-names = "default";

        pinctrl-0 = <&pinctrl_gpio0_default>;

};



&uart1 {

	status = "okay";

	pinctrl-names = "default";

arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso

+25 −0
Original line number Diff line number Diff line
@@ -152,6 +152,25 @@ phy0: ethernet-phy@1 { 
&pinctrl0 {

	status = "okay";



	pinctrl_gpio0_default: gpio0-default {

		conf {

			groups = "gpio0_38_grp";

			bias-pull-up;

			power-source = <IO_STANDARD_LVCMOS18>;

		};



		mux {

			groups = "gpio0_38_grp";

			function = "gpio0";

		};



		conf-tx {

			pins = "MIO38";

			bias-disable;

			output-enable;

		};

	};



	pinctrl_uart1_default: uart1-default {

		conf {

			groups = "uart1_9_grp";
@@ -307,6 +326,12 @@ mux { 
	};

};



&gpio {

	status = "okay";

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_gpio0_default>;

};



&uart1 {

	status = "okay";

	pinctrl-names = "default";