Commit ea89b305 authored by Jay Cornwall's avatar Jay Cornwall Committed by Alex Deucher
Browse files

drm/amdkfd: Fix scalar load ordering in gfx12.1 trap handler



Scalar loads may arrive out-of-order with respect to KMCNT.
The affected code expects the two loads to arrive in-order.

Signed-off-by: default avatarJay Cornwall <jay.cornwall@amd.com>
Reviewed-by: default avatarLancelot Six <lancelot.six@amd.com>
Cc: Joseph Greathouse <joseph.greathouse@amd.com>
Cc: Vladimir Indic <vladimir.indic@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d9fc0bdf
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+4 −4
Original line number Diff line number Diff line
@@ -4638,8 +4638,8 @@ static const uint32_t cwsr_trap_gfx12_1_0_hex[] = {
	0x01ffffff, 0xb8fbf811,
	0xbf0d847b, 0xbfa20078,
	0xf4003eb6, 0xf8000000,
	0xf4003bb6, 0xf8000008,
	0xbfc70001, 0x8b76ff7a,
	0xbfc70000, 0xf4003bb6,
	0xf8000008, 0x8b76ff7a,
	0x80000000, 0xbfa20027,
	0x9376ff7a, 0x00060019,
	0x81f9a376, 0xbf0b8179,
@@ -4717,8 +4717,8 @@ static const uint32_t cwsr_trap_gfx12_1_0_hex[] = {
	0xb980f821, 0x00000000,
	0xbf0d847b, 0xbfa20078,
	0xf4003eb6, 0xf8000000,
	0xf4003bb6, 0xf8000008,
	0xbfc70001, 0x8b76ff7a,
	0xbfc70000, 0xf4003bb6,
	0xf8000008, 0x8b76ff7a,
	0x80000000, 0xbfa20027,
	0x9376ff7a, 0x00060019,
	0x81f9a376, 0xbf0b8179,
+1 −1
Original line number Diff line number Diff line
@@ -1355,8 +1355,8 @@ function fixup_vgpr_bank_selection
	// ttmp[0:1]: {7b'0} PC[56:0]
	// ttmp2, 3, 10, 13, 14, 15: free
	s_load_b64	[ttmp14, ttmp15], [ttmp0, ttmp1], 0 scope:SCOPE_CU	// Load the 2 instruction DW we are returning to
	s_wait_kmcnt	0
	s_load_b64	[ttmp2, ttmp3], [ttmp0, ttmp1], 8 scope:SCOPE_CU	// Load the next 2 instruction DW, just in case
	s_wait_kmcnt	1
	s_and_b32	ttmp10, ttmp14, 0x80000000				// Check bit 31 in the first DWORD
										// SCC set if ttmp10 is != 0, i.e. if bit 31 == 1
	s_cbranch_scc1	L_FIXUP_NOT_VOP12C					// If bit 31 is 1, we are not VOP1, VOP2, or VOP3C