Commit eb226631 authored by Usama Arif's avatar Usama Arif Committed by Borislav Petkov (AMD)
Browse files

x86/boot: Fix page table access in 5-level to 4-level paging transition 



When transitioning from 5-level to 4-level paging, the existing code
incorrectly accesses page table entries by directly dereferencing CR3 and
applying PAGE_MASK. This approach has several issues:

- __native_read_cr3() returns the raw CR3 register value, which on x86_64
  includes not just the physical address but also flags. Bits above the
  physical address width of the system i.e. above __PHYSICAL_MASK_SHIFT) are
  also not masked.

- The PGD entry is masked by PAGE_SIZE which doesn't take into account the
  higher bits such as _PAGE_BIT_NOPTISHADOW.

Replace this with proper accessor functions:

- native_read_cr3_pa(): Uses CR3_ADDR_MASK to additionally mask metadata out
  of CR3 (like SME or LAM bits). All remaining bits are real address bits or
  reserved and must be 0.

- mask pgd value with PTE_PFN_MASK instead of PAGE_MASK, accounting for flags
  above bit 51 (_PAGE_BIT_NOPTISHADOW in particular). Bits below 51, but above
  the max physical address are reserved and must be 0.

Fixes: e9d0e633 ("x86/boot/compressed/64: Prepare new top-level page table for trampoline")
Reported-by: default avatarMichael van der Westhuizen <rmikey@meta.com>
Reported-by: default avatarTobias Fleig <tfleig@meta.com>
Co-developed-by: default avatarKiryl Shutsemau <kas@kernel.org>
Signed-off-by: default avatarKiryl Shutsemau <kas@kernel.org>
Signed-off-by: default avatarUsama Arif <usamaarif642@gmail.com>
Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: default avatarArd Biesheuvel <ardb@kernel.org>
Acked-by: default avatarDave Hansen <dave.hansen@linux.intel.com>
Link: https://lore.kernel.org/r/a482fd68-ce54-472d-8df1-33d6ac9f6bb5@intel.com
parent 5385dec7

arch/x86/boot/compressed/pgtable_64.c

+7 −4
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ 
#include <asm/bootparam.h>

#include <asm/bootparam_utils.h>

#include <asm/e820/types.h>

#include <asm/pgtable.h>

#include <asm/processor.h>

#include "../string.h"

#include "efi.h"
@@ -168,9 +169,10 @@ asmlinkage void configure_5level_paging(struct boot_params *bp, void *pgtable) 
		 * For 4- to 5-level paging transition, set up current CR3 as

		 * the first and the only entry in a new top-level page table.

		 */

		*trampoline_32bit = __native_read_cr3() | _PAGE_TABLE_NOENC;

		*trampoline_32bit = native_read_cr3_pa() | _PAGE_TABLE_NOENC;

	} else {

		unsigned long src;

		u64 *new_cr3;

		pgd_t *pgdp;



		/*

		 * For 5- to 4-level paging transition, copy page table pointed
@@ -180,8 +182,9 @@ asmlinkage void configure_5level_paging(struct boot_params *bp, void *pgtable) 
		 * We cannot just point to the page table from trampoline as it

		 * may be above 4G.

		 */

		src = *(unsigned long *)__native_read_cr3() & PAGE_MASK;

		memcpy(trampoline_32bit, (void *)src, PAGE_SIZE);

		pgdp = (pgd_t *)native_read_cr3_pa();

		new_cr3 = (u64 *)(native_pgd_val(pgdp[0]) & PTE_PFN_MASK);

		memcpy(trampoline_32bit, new_cr3, PAGE_SIZE);

	}



	toggle_la57(trampoline_32bit);