Commit eb69e001 authored by Boris Brezillon's avatar Boris Brezillon Committed by Gregory CLEMENT
Browse files

ARM: mvebu: use new bindings for existing crypto devices 



The new bindings split the crypto and sram node in two separate devices.
Modify the existing crypto nodes to match the new representation.

Signed-off-by: default avatarBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: default avatarGregory CLEMENT <gregory.clement@free-electrons.com>
parent d716f2e8

arch/arm/boot/dts/dove.dtsi

+12 −3
Original line number Diff line number Diff line
@@ -264,11 +264,12 @@ watchdog@20300 { 


			crypto: crypto-engine@30000 {

				compatible = "marvell,orion-crypto";

				reg = <0x30000 0x10000>,

				      <0xffffe000 0x800>;

				reg-names = "regs", "sram";

				reg = <0x30000 0x10000>;

				reg-names = "regs";

				interrupts = <31>;

				clocks = <&gate_clk 15>;

				marvell,crypto-srams = <&crypto_sram>;

				marvell,crypto-sram-size = <0x800>;

				status = "okay";

			};
@@ -767,6 +768,14 @@ lcd0: lcd-controller@820000 { 
				interrupts = <47>;

				status = "disabled";

			};



			crypto_sram: sa-sram@ffffe000 {

				compatible = "mmio-sram";

				reg = <0xffffe000 0x800>;

				clocks = <&gate_clk 15>;

				#address-cells = <1>;

				#size-cells = <1>;

			};

		};

	};

};

arch/arm/boot/dts/kirkwood.dtsi

+19 −10
Original line number Diff line number Diff line
@@ -40,16 +40,6 @@ MBUS_ID(0x03, 0x01) 0 0xf5000000 0x10000 /* crypto sram */ 
		pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */

		pcie-io-aperture  = <0xf2000000 0x100000>;   /*   1 MiB    I/O space */



		cesa: crypto@0301 {

			compatible = "marvell,orion-crypto";

			reg = <MBUS_ID(0xf0, 0x01) 0x30000 0x10000>,

			      <MBUS_ID(0x03, 0x01) 0 0x800>;

			reg-names = "regs", "sram";

			interrupts = <22>;

			clocks = <&gate_clk 17>;

			status = "okay";

		};



		nand: nand@012f {

			#address-cells = <1>;

			#size-cells = <1>;
@@ -65,6 +55,14 @@ nand: nand@012f { 
			pinctrl-names = "default";

			status = "disabled";

		};



		crypto_sram: sa-sram@0301 {

			compatible = "mmio-sram";

			reg = <MBUS_ID(0x03, 0x01) 0x0 0x800>;

			clocks = <&gate_clk 17>;

			#address-cells = <1>;

			#size-cells = <1>;

		};

	};



	ocp@f1000000 {
@@ -252,6 +250,17 @@ wdt: watchdog-timer@20300 { 
			status = "okay";

		};



		cesa: crypto@30000 {

			compatible = "marvell,orion-crypto";

			reg = <0x30000 0x10000>;

			reg-names = "regs";

			interrupts = <22>;

			clocks = <&gate_clk 17>;

			marvell,crypto-srams = <&crypto_sram>;

			marvell,crypto-sram-size = <0x800>;

			status = "okay";

		};



		usb0: ehci@50000 {

			compatible = "marvell,orion-ehci";

			reg = <0x50000 0x1000>;

arch/arm/boot/dts/orion5x.dtsi

+15 −7
Original line number Diff line number Diff line
@@ -212,6 +212,16 @@ sata: sata@80000 { 
				status = "disabled";

			};



			cesa: crypto@90000 {

				compatible = "marvell,orion-crypto";

				reg = <0x90000 0x10000>;

				reg-names = "regs";

				interrupts = <28>;

				marvell,crypto-srams = <&crypto_sram>;

				marvell,crypto-sram-size = <0x800>;

				status = "okay";

			};



			ehci1: ehci@a0000 {

				compatible = "marvell,orion-ehci";

				reg = <0xa0000 0x1000>;
@@ -220,13 +230,11 @@ ehci1: ehci@a0000 { 
			};

		};



		cesa: crypto@90000 {

			compatible = "marvell,orion-crypto";

			reg = <MBUS_ID(0xf0, 0x01) 0x90000 0x10000>,

			      <MBUS_ID(0x09, 0x00) 0x0 0x800>;

			reg-names = "regs", "sram";

			interrupts = <28>;

			status = "okay";

		crypto_sram: sa-sram {

			compatible = "mmio-sram";

			reg = <MBUS_ID(0x09, 0x00) 0x0 0x800>;

			#address-cells = <1>;

			#size-cells = <1>;

		};

	};

};