Commit eba791dc authored by Shane Xiao's avatar Shane Xiao Committed by Alex Deucher
Browse files

drm/amdgpu: Update the impelmentation of AMDGPU_PTE_MTYPE_GFX12 



This patch changes the implementation of AMDGPU_PTE_MTYPE_GFX12,
clear the bits before setting the new one.
This fixed the potential issue that GFX12 setting memory to NC.

v2: Clear mtype field before setting the new one (Alex)
v3: Fix typo (Felix)

Suggested-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarlonglyao <Longlong.Yao@amd.com>
Signed-off-by: default avatarShane Xiao <shane.xiao@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f8718c48

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h

+5 −2
Original line number Diff line number Diff line
@@ -116,8 +116,11 @@ struct amdgpu_mem_stats; 
#define AMDGPU_PTE_PRT_FLAG(adev)	\

	((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PTE_PRT_GFX12 : AMDGPU_PTE_PRT)



#define AMDGPU_PTE_MTYPE_GFX12(a)	((uint64_t)(a) << 54)

#define AMDGPU_PTE_MTYPE_GFX12_MASK	AMDGPU_PTE_MTYPE_GFX12(3ULL)

#define AMDGPU_PTE_MTYPE_GFX12_SHIFT(mtype)	((uint64_t)(mtype) << 54)

#define AMDGPU_PTE_MTYPE_GFX12_MASK	AMDGPU_PTE_MTYPE_GFX12_SHIFT(3ULL)

#define AMDGPU_PTE_MTYPE_GFX12(flags, mtype)				\

	(((uint64_t)(flags) & (~AMDGPU_PTE_MTYPE_GFX12_MASK)) |	\

	  AMDGPU_PTE_MTYPE_GFX12_SHIFT(mtype))



#define AMDGPU_PTE_IS_PTE		(1ULL << 63)

drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c

+9 −10
Original line number Diff line number Diff line
@@ -461,17 +461,17 @@ static uint64_t gmc_v12_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 
{

	switch (flags) {

	case AMDGPU_VM_MTYPE_DEFAULT:

		return AMDGPU_PTE_MTYPE_GFX12(MTYPE_NC);

		return AMDGPU_PTE_MTYPE_GFX12(0ULL, MTYPE_NC);

	case AMDGPU_VM_MTYPE_NC:

		return AMDGPU_PTE_MTYPE_GFX12(MTYPE_NC);

		return AMDGPU_PTE_MTYPE_GFX12(0ULL, MTYPE_NC);

	case AMDGPU_VM_MTYPE_WC:

		return AMDGPU_PTE_MTYPE_GFX12(MTYPE_WC);

		return AMDGPU_PTE_MTYPE_GFX12(0ULL, MTYPE_WC);

	case AMDGPU_VM_MTYPE_CC:

		return AMDGPU_PTE_MTYPE_GFX12(MTYPE_CC);

		return AMDGPU_PTE_MTYPE_GFX12(0ULL, MTYPE_CC);

	case AMDGPU_VM_MTYPE_UC:

		return AMDGPU_PTE_MTYPE_GFX12(MTYPE_UC);

		return AMDGPU_PTE_MTYPE_GFX12(0ULL, MTYPE_UC);

	default:

		return AMDGPU_PTE_MTYPE_GFX12(MTYPE_NC);

		return AMDGPU_PTE_MTYPE_GFX12(0ULL, MTYPE_NC);

	}

}
@@ -524,8 +524,7 @@ static void gmc_v12_0_get_vm_pte(struct amdgpu_device *adev, 


	if (bo->flags & (AMDGPU_GEM_CREATE_COHERENT |

			       AMDGPU_GEM_CREATE_UNCACHED))

		*flags = (*flags & ~AMDGPU_PTE_MTYPE_GFX12_MASK) |

			 AMDGPU_PTE_MTYPE_GFX12(MTYPE_UC);

		*flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_UC);



	bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);

	coherent = bo->flags & AMDGPU_GEM_CREATE_COHERENT;
@@ -534,7 +533,7 @@ static void gmc_v12_0_get_vm_pte(struct amdgpu_device *adev, 


	/* WA for HW bug */

	if (is_system || ((bo_adev != adev) && coherent))

		*flags |= AMDGPU_PTE_MTYPE_GFX12(MTYPE_NC);

		*flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_NC);



}
@@ -707,7 +706,7 @@ static int gmc_v12_0_gart_init(struct amdgpu_device *adev) 
		return r;



	adev->gart.table_size = adev->gart.num_gpu_pages * 8;

	adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_GFX12(MTYPE_UC) |

	adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_GFX12(0ULL, MTYPE_UC) |

				    AMDGPU_PTE_EXECUTABLE |

				    AMDGPU_PTE_IS_PTE;