Commit ebd38b26 authored by Paolo Bonzini's avatar Paolo Bonzini
Browse files

Merge tag 'kvm-x86-misc-6.16' of https://github.com/kvm-x86/linux into HEAD 

KVM x86 misc changes for 6.16:

 - Unify virtualization of IBRS on nested VM-Exit, and cross-vCPU IBPB, between
   SVM and VMX.

 - Advertise support to userspace for WRMSRNS and PREFETCHI.

 - Rescan I/O APIC routes after handling EOI that needed to be intercepted due
   to the old/previous routing, but not the new/current routing.

 - Add a module param to control and enumerate support for device posted
   interrupts.

 - Misc cleanups.
parents cd1be30b 37d8bad4

arch/x86/include/asm/cpufeatures.h

+2 −0
Original line number Diff line number Diff line
@@ -336,6 +336,7 @@ 
#define X86_FEATURE_AMD_IBRS		(13*32+14) /* Indirect Branch Restricted Speculation */

#define X86_FEATURE_AMD_STIBP		(13*32+15) /* Single Thread Indirect Branch Predictors */

#define X86_FEATURE_AMD_STIBP_ALWAYS_ON	(13*32+17) /* Single Thread Indirect Branch Predictors always-on preferred */

#define X86_FEATURE_AMD_IBRS_SAME_MODE	(13*32+19) /* Indirect Branch Restricted Speculation same mode protection*/

#define X86_FEATURE_AMD_PPIN		(13*32+23) /* "amd_ppin" Protected Processor Inventory Number */

#define X86_FEATURE_AMD_SSBD		(13*32+24) /* Speculative Store Bypass Disable */

#define X86_FEATURE_VIRT_SSBD		(13*32+25) /* "virt_ssbd" Virtualized Speculative Store Bypass Disable */
@@ -457,6 +458,7 @@ 
#define X86_FEATURE_AUTOIBRS		(20*32+ 8) /* Automatic IBRS */

#define X86_FEATURE_NO_SMM_CTL_MSR	(20*32+ 9) /* SMM_CTL MSR is not present */



#define X86_FEATURE_PREFETCHI		(20*32+20) /* Prefetch Data/Instruction to Cache Level */

#define X86_FEATURE_SBPB		(20*32+27) /* Selective Branch Prediction Barrier */

#define X86_FEATURE_IBPB_BRTYPE		(20*32+28) /* MSR_PRED_CMD[IBPB] flushes all branch type predictions */

#define X86_FEATURE_SRSO_NO		(20*32+29) /* CPU is not affected by SRSO */

arch/x86/include/asm/kvm_host.h

+3 −1
Original line number Diff line number Diff line
@@ -1034,6 +1034,7 @@ struct kvm_vcpu_arch { 


	int pending_ioapic_eoi;

	int pending_external_vector;

	int highest_stale_pending_ioapic_eoi;



	/* be preempted when it's in kernel-mode(cpl=0) */

	bool preempted_in_kernel;
@@ -1941,6 +1942,7 @@ struct kvm_arch_async_pf { 
extern u32 __read_mostly kvm_nr_uret_msrs;

extern bool __read_mostly allow_smaller_maxphyaddr;

extern bool __read_mostly enable_apicv;

extern bool __read_mostly enable_device_posted_irqs;

extern struct kvm_x86_ops kvm_x86_ops;



#define kvm_x86_call(func) static_call(kvm_x86_##func)
@@ -2444,7 +2446,7 @@ int memslot_rmap_alloc(struct kvm_memory_slot *slot, unsigned long npages); 


static inline bool kvm_arch_has_irq_bypass(void)

{

	return enable_apicv && irq_remapping_cap(IRQ_POSTING_CAP);

	return enable_device_posted_irqs;

}



#endif /* _ASM_X86_KVM_HOST_H */

arch/x86/include/asm/msr.h

+2 −2
Original line number Diff line number Diff line
@@ -300,7 +300,7 @@ do { \ 
#endif	/* !CONFIG_PARAVIRT_XXL */



/* Instruction opcode for WRMSRNS supported in binutils >= 2.40 */

#define WRMSRNS _ASM_BYTES(0x0f,0x01,0xc6)

#define ASM_WRMSRNS _ASM_BYTES(0x0f,0x01,0xc6)



/* Non-serializing WRMSR, when available.  Falls back to a serializing WRMSR. */

static __always_inline void wrmsrns(u32 msr, u64 val)
@@ -309,7 +309,7 @@ static __always_inline void wrmsrns(u32 msr, u64 val) 
	 * WRMSR is 2 bytes.  WRMSRNS is 3 bytes.  Pad WRMSR with a redundant

	 * DS prefix to avoid a trailing NOP.

	 */

	asm volatile("1: " ALTERNATIVE("ds wrmsr", WRMSRNS, X86_FEATURE_WRMSRNS)

	asm volatile("1: " ALTERNATIVE("ds wrmsr", ASM_WRMSRNS, X86_FEATURE_WRMSRNS)

		     "2: " _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_WRMSR)

		     : : "c" (msr), "a" ((u32)val), "d" ((u32)(val >> 32)));

}

arch/x86/kvm/cpuid.c

+7 −1
Original line number Diff line number Diff line
@@ -978,6 +978,7 @@ void kvm_set_cpu_caps(void) 
		F(FZRM),

		F(FSRS),

		F(FSRC),

		F(WRMSRNS),

		F(AMX_FP16),

		F(AVX_IFMA),

		F(LAM),
@@ -1093,6 +1094,7 @@ void kvm_set_cpu_caps(void) 
		F(AMD_SSB_NO),

		F(AMD_STIBP),

		F(AMD_STIBP_ALWAYS_ON),

		F(AMD_IBRS_SAME_MODE),

		F(AMD_PSFD),

		F(AMD_IBPB_RET),

	);
@@ -1150,6 +1152,7 @@ void kvm_set_cpu_caps(void) 


	kvm_cpu_cap_init(CPUID_8000_0021_EAX,

		F(NO_NESTED_DATA_BP),

		F(WRMSR_XX_BASE_NS),

		/*

		 * Synthesize "LFENCE is serializing" into the AMD-defined entry

		 * in KVM's supported CPUID, i.e. if the feature is reported as
@@ -1163,10 +1166,13 @@ void kvm_set_cpu_caps(void) 
		SYNTHESIZED_F(LFENCE_RDTSC),

		/* SmmPgCfgLock */

		F(NULL_SEL_CLR_BASE),

		/* UpperAddressIgnore */

		F(AUTOIBRS),

		F(PREFETCHI),

		EMULATED_F(NO_SMM_CTL_MSR),

		/* PrefetchCtlMsr */

		F(WRMSR_XX_BASE_NS),

		/* GpOnUserCpuid */

		/* EPSF */

		SYNTHESIZED_F(SBPB),

		SYNTHESIZED_F(IBPB_BRTYPE),

		SYNTHESIZED_F(SRSO_NO),

arch/x86/kvm/ioapic.c

+2 −5
Original line number Diff line number Diff line
@@ -296,11 +296,8 @@ void kvm_ioapic_scan_entry(struct kvm_vcpu *vcpu, ulong *ioapic_handled_vectors) 
		    index == RTC_GSI) {

			u16 dm = kvm_lapic_irq_dest_mode(!!e->fields.dest_mode);



			if (kvm_apic_match_dest(vcpu, NULL, APIC_DEST_NOSHORT,

						e->fields.dest_id, dm) ||

			    kvm_apic_pending_eoi(vcpu, e->fields.vector))

				__set_bit(e->fields.vector,

					  ioapic_handled_vectors);

			kvm_scan_ioapic_irq(vcpu, e->fields.dest_id, dm,

					    e->fields.vector, ioapic_handled_vectors);

		}

	}

	spin_unlock(&ioapic->lock);