riscv: Add support for kernel mode vector (ecd2ada8) · Commits · git / linux-nf

arch/riscv/include/asm/processor.h

+11 −1

Original line number	Diff line number	Diff line
		@@ -73,6 +73,15 @@
		struct task_struct;
		struct pt_regs;

		/*
		* We use a flag to track in-kernel Vector context. Currently the flag has the
		* following meaning:
		*
		* - bit 0: indicates whether the in-kernel Vector context is active. The
		* activation of this state disables the preemption.
		*/
		#define RISCV_KERNEL_MODE_V 0x1

		/* CPU-specific state of a task */
		struct thread_struct {
		/* Callee-saved registers */
		@@ -81,7 +90,8 @@ struct thread_struct {
		unsigned long s[12]; /* s[0]: frame pointer */
		struct __riscv_d_ext_state fstate;
		unsigned long bad_cause;
		unsigned long vstate_ctrl;
		u32 riscv_v_flags;
		u32 vstate_ctrl;
		struct __riscv_v_ext_state vstate;
		unsigned long align_ctl;
		};

arch/riscv/include/asm/simd.h

0 → 100644

+44 −0

Original line number	Diff line number	Diff line
		/* SPDX-License-Identifier: GPL-2.0-only */
		/*
		* Copyright (C) 2017 Linaro Ltd. <ard.biesheuvel@linaro.org>
		* Copyright (C) 2023 SiFive
		*/

		#ifndef __ASM_SIMD_H
		#define __ASM_SIMD_H

		#include <linux/compiler.h>
		#include <linux/irqflags.h>
		#include <linux/percpu.h>
		#include <linux/preempt.h>
		#include <linux/types.h>

		#include <asm/vector.h>

		#ifdef CONFIG_RISCV_ISA_V
		/*
		* may_use_simd - whether it is allowable at this time to issue vector
		* instructions or access the vector register file
		*
		* Callers must not assume that the result remains true beyond the next
		* preempt_enable() or return from softirq context.
		*/
		static __must_check inline bool may_use_simd(void)
		{
		/*
		* RISCV_KERNEL_MODE_V is only set while preemption is disabled,
		* and is clear whenever preemption is enabled.
		*/
		return !in_hardirq() && !in_nmi() && !(riscv_v_flags() & RISCV_KERNEL_MODE_V);
		}

		#else /* ! CONFIG_RISCV_ISA_V */

		static __must_check inline bool may_use_simd(void)
		{
		return false;
		}

		#endif /* ! CONFIG_RISCV_ISA_V */

		#endif

arch/riscv/include/asm/vector.h

+9 −0

Original line number	Diff line number	Diff line
		@@ -22,6 +22,15 @@
		extern unsigned long riscv_v_vsize;
		int riscv_v_setup_vsize(void);
		bool riscv_v_first_use_handler(struct pt_regs *regs);
		void kernel_vector_begin(void);
		void kernel_vector_end(void);
		void get_cpu_vector_context(void);
		void put_cpu_vector_context(void);

		static inline u32 riscv_v_flags(void)
		{
		return current->thread.riscv_v_flags;
		}

		static __always_inline bool has_vector(void)
		{

arch/riscv/kernel/Makefile

+1 −0

Original line number	Diff line number	Diff line
		@@ -63,6 +63,7 @@ obj-$(CONFIG_MMU) += vdso.o vdso/
		obj-$(CONFIG_RISCV_MISALIGNED) += traps_misaligned.o
		obj-$(CONFIG_FPU) += fpu.o
		obj-$(CONFIG_RISCV_ISA_V) += vector.o
		obj-$(CONFIG_RISCV_ISA_V) += kernel_mode_vector.o
		obj-$(CONFIG_SMP) += smpboot.o
		obj-$(CONFIG_SMP) += smp.o
		obj-$(CONFIG_SMP) += cpu_ops.o

arch/riscv/kernel/kernel_mode_vector.c

0 → 100644

+116 −0

Original line number	Diff line number	Diff line
		// SPDX-License-Identifier: GPL-2.0-or-later
		/*
		* Copyright (C) 2012 ARM Ltd.
		* Author: Catalin Marinas <catalin.marinas@arm.com>
		* Copyright (C) 2017 Linaro Ltd. <ard.biesheuvel@linaro.org>
		* Copyright (C) 2021 SiFive
		*/
		#include <linux/compiler.h>
		#include <linux/irqflags.h>
		#include <linux/percpu.h>
		#include <linux/preempt.h>
		#include <linux/types.h>

		#include <asm/vector.h>
		#include <asm/switch_to.h>
		#include <asm/simd.h>

		static inline void riscv_v_flags_set(u32 flags)
		{
		current->thread.riscv_v_flags = flags;
		}

		static inline void riscv_v_start(u32 flags)
		{
		int orig;

		orig = riscv_v_flags();
		BUG_ON((orig & flags) != 0);
		riscv_v_flags_set(orig \| flags);
		}

		static inline void riscv_v_stop(u32 flags)
		{
		int orig;

		orig = riscv_v_flags();
		BUG_ON((orig & flags) == 0);
		riscv_v_flags_set(orig & ~flags);
		}

		/*
		* Claim ownership of the CPU vector context for use by the calling context.
		*
		* The caller may freely manipulate the vector context metadata until
		* put_cpu_vector_context() is called.
		*/
		void get_cpu_vector_context(void)
		{
		preempt_disable();

		riscv_v_start(RISCV_KERNEL_MODE_V);
		}

		/*
		* Release the CPU vector context.
		*
		* Must be called from a context in which get_cpu_vector_context() was
		* previously called, with no call to put_cpu_vector_context() in the
		* meantime.
		*/
		void put_cpu_vector_context(void)
		{
		riscv_v_stop(RISCV_KERNEL_MODE_V);

		preempt_enable();
		}

		/*
		* kernel_vector_begin(): obtain the CPU vector registers for use by the calling
		* context
		*
		* Must not be called unless may_use_simd() returns true.
		* Task context in the vector registers is saved back to memory as necessary.
		*
		* A matching call to kernel_vector_end() must be made before returning from the
		* calling context.
		*
		* The caller may freely use the vector registers until kernel_vector_end() is
		* called.
		*/
		void kernel_vector_begin(void)
		{
		if (WARN_ON(!has_vector()))
		return;

		BUG_ON(!may_use_simd());

		get_cpu_vector_context();

		riscv_v_vstate_save(current, task_pt_regs(current));

		riscv_v_enable();
		}
		EXPORT_SYMBOL_GPL(kernel_vector_begin);

		/*
		* kernel_vector_end(): give the CPU vector registers back to the current task
		*
		* Must be called from a context in which kernel_vector_begin() was previously
		* called, with no call to kernel_vector_end() in the meantime.
		*
		* The caller must not use the vector registers after this function is called,
		* unless kernel_vector_begin() is called again in the meantime.
		*/
		void kernel_vector_end(void)
		{
		if (WARN_ON(!has_vector()))
		return;

		riscv_v_vstate_restore(current, task_pt_regs(current));

		riscv_v_disable();

		put_cpu_vector_context();
		}
		EXPORT_SYMBOL_GPL(kernel_vector_end);