Unverified Commit eddbfa0d authored by Clément Léger's avatar Clément Léger Committed by Palmer Dabbelt
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riscv: add ISA extension parsing for Zihintntl 

Add parsing for Zihintntl ISA extension[1] that was ratified in commit
0dc91f5 ("Zihintntl is ratified") of riscv-isa-manual[2].

Link: https://drive.google.com/file/d/13_wsN8YmRfH8YWysFyTX-DjTkCnBd9hj/view [1]
Link: https://github.com/riscv/riscv-isa-manual/commit/0dc91f505e6d

 [2]
Signed-off-by: default avatarClément Léger <cleger@rivosinc.com>
Reviewed-by: default avatarEvan Green <evan@rivosinc.com>
Link: https://lore.kernel.org/r/20231114141256.126749-13-cleger@rivosinc.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent c44714c3

arch/riscv/include/asm/hwcap.h

+1 −0
Original line number Diff line number Diff line
@@ -80,6 +80,7 @@ 
#define RISCV_ISA_EXT_ZVKT		65

#define RISCV_ISA_EXT_ZFH		66

#define RISCV_ISA_EXT_ZFHMIN		67

#define RISCV_ISA_EXT_ZIHINTNTL		68



#define RISCV_ISA_EXT_MAX		128

#define RISCV_ISA_EXT_INVALID		U32_MAX

arch/riscv/kernel/cpufeature.c

+1 −0
Original line number Diff line number Diff line
@@ -256,6 +256,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { 
	__RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND),

	__RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR),

	__RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI),

	__RISCV_ISA_EXT_DATA(zihintntl, RISCV_ISA_EXT_ZIHINTNTL),

	__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),

	__RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM),

	__RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH),