Commit ee06c09d authored by Matthew Auld's avatar Matthew Auld Committed by Lucas De Marchi
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drm/xe/vram: fix ccs offset calculation 



Spec says SW is expected to round up to the nearest 128K, if not already
aligned for the CC unit view of CCS. We are seeing the assert sometimes
pop on BMG to tell us that there is a hole between GSM and CCS, as well
as popping other asserts with having a vram size with strange alignment,
which is likely caused by misaligned offset here.

v2 (Shuicheng):
 - Do the round_up() on final SW address.

BSpec: 68023
Fixes: b5c2ca03 ("drm/xe/xe2hpg: Determine flat ccs offset for vram")
Signed-off-by: default avatarMatthew Auld <matthew.auld@intel.com>
Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Cc: Akshata Jahagirdar <akshata.jahagirdar@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Shuicheng Lin <shuicheng.lin@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: stable@vger.kernel.org # v6.10+
Reviewed-by: default avatarHimal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Tested-by: default avatarShuicheng Lin <shuicheng.lin@intel.com>
Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240916084911.13119-2-matthew.auld@intel.com


Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
(cherry picked from commit 37173392)
Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
parent 7ab9ebc5

drivers/gpu/drm/xe/xe_vram.c

+1 −0
Original line number Diff line number Diff line
@@ -182,6 +182,7 @@ static inline u64 get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size) 
		offset = offset_hi << 32; /* HW view bits 39:32 */

		offset |= offset_lo << 6; /* HW view bits 31:6 */

		offset *= num_enabled; /* convert to SW view */

		offset = round_up(offset, SZ_128K); /* SW must round up to nearest 128K */



		/* We don't expect any holes */

		xe_assert_msg(xe, offset == (xe_mmio_read64_2x32(gt, GSMBASE) - ccs_size),