Commit ee0a469c authored by Jonathan Kim's avatar Jonathan Kim Committed by Alex Deucher
Browse files

drm/amdkfd: support per-queue reset on gfx9 



Support per-queue reset for GFX9.  The recommendation is for the driver
to target reset the HW queue via a SPI MMIO register write.

Since this requires pipe and HW queue info and MEC FW is limited to
doorbell reports of hung queues after an unmap failure, scan the HW
queue slots defined by SET_RESOURCES first to identify the user queue
candidates to reset.

Only signal reset events to processes that have had a queue reset.

If queue reset fails, fall back to GPU reset.

Signed-off-by: default avatarJonathan Kim <jonathan.kim@amd.com>
Reviewed-by: default avatarFelix Kuehling <felix.kuehling@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e89d2fec

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

+2 −0
Original line number Diff line number Diff line
@@ -191,4 +191,6 @@ const struct kfd2kgd_calls aldebaran_kfd2kgd = { 
	.get_iq_wait_times = kgd_gfx_v9_get_iq_wait_times,

	.build_grace_period_packet_info = kgd_gfx_v9_build_grace_period_packet_info,

	.program_trap_handler_settings = kgd_gfx_v9_program_trap_handler_settings,

	.hqd_get_pq_addr = kgd_gfx_v9_hqd_get_pq_addr,

	.hqd_reset = kgd_gfx_v9_hqd_reset,

};

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

+3 −1
Original line number Diff line number Diff line
@@ -418,5 +418,7 @@ const struct kfd2kgd_calls arcturus_kfd2kgd = { 
	.get_iq_wait_times = kgd_gfx_v9_get_iq_wait_times,

	.build_grace_period_packet_info = kgd_gfx_v9_build_grace_period_packet_info,

	.get_cu_occupancy = kgd_gfx_v9_get_cu_occupancy,

	.program_trap_handler_settings = kgd_gfx_v9_program_trap_handler_settings

	.program_trap_handler_settings = kgd_gfx_v9_program_trap_handler_settings,

	.hqd_get_pq_addr = kgd_gfx_v9_hqd_get_pq_addr,

	.hqd_reset = kgd_gfx_v9_hqd_reset

};

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

+3 −1
Original line number Diff line number Diff line
@@ -541,5 +541,7 @@ const struct kfd2kgd_calls gc_9_4_3_kfd2kgd = { 
			kgd_gfx_v9_4_3_set_wave_launch_trap_override,

	.set_wave_launch_mode = kgd_aldebaran_set_wave_launch_mode,

	.set_address_watch = kgd_gfx_v9_4_3_set_address_watch,

	.clear_address_watch = kgd_gfx_v9_4_3_clear_address_watch

	.clear_address_watch = kgd_gfx_v9_4_3_clear_address_watch,

	.hqd_get_pq_addr = kgd_gfx_v9_hqd_get_pq_addr,

	.hqd_reset = kgd_gfx_v9_hqd_reset

};

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

+16 −0
Original line number Diff line number Diff line
@@ -1070,6 +1070,20 @@ static void program_trap_handler_settings(struct amdgpu_device *adev, 
	unlock_srbm(adev);

}



uint64_t kgd_gfx_v10_hqd_get_pq_addr(struct amdgpu_device *adev,

				     uint32_t pipe_id, uint32_t queue_id,

				     uint32_t inst)

{

	return 0;

}



uint64_t kgd_gfx_v10_hqd_reset(struct amdgpu_device *adev,

			       uint32_t pipe_id, uint32_t queue_id,

			       uint32_t inst, unsigned int utimeout)

{

	return 0;

}



const struct kfd2kgd_calls gfx_v10_kfd2kgd = {

	.program_sh_mem_settings = kgd_program_sh_mem_settings,

	.set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
@@ -1097,4 +1111,6 @@ const struct kfd2kgd_calls gfx_v10_kfd2kgd = { 
	.get_iq_wait_times = kgd_gfx_v10_get_iq_wait_times,

	.build_grace_period_packet_info = kgd_gfx_v10_build_grace_period_packet_info,

	.program_trap_handler_settings = program_trap_handler_settings,

	.hqd_get_pq_addr = kgd_gfx_v10_hqd_get_pq_addr,

	.hqd_reset = kgd_gfx_v10_hqd_reset

};

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

+9 −0
Original line number Diff line number Diff line
@@ -56,3 +56,12 @@ void kgd_gfx_v10_build_grace_period_packet_info(struct amdgpu_device *adev, 
					       uint32_t grace_period,

					       uint32_t *reg_offset,

					       uint32_t *reg_data);

uint64_t kgd_gfx_v10_hqd_get_pq_addr(struct amdgpu_device *adev,

				    uint32_t pipe_id,

				    uint32_t queue_id,

				    uint32_t inst);

uint64_t kgd_gfx_v10_hqd_reset(struct amdgpu_device *adev,

			      uint32_t pipe_id,

			      uint32_t queue_id,

			      uint32_t inst,

			      unsigned int utimeout);