Commit ee26c3b2 authored by Niranjana Vishwanathapura's avatar Niranjana Vishwanathapura
Browse files

drm/xe/multi_queue: Add multi_queue_enable_mask to gt information 



Add multi_queue_enable_mask field to the gt information structure
which is bitmask of all engine classes with multi queue support
enabled.

v2: Rename multi_queue_enable_mask to multi_queue_engine_class_mask
    (Matt Brost)

Signed-off-by: default avatarNiranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Reviewed-by: default avatarMatthew Brost <matthew.brost@intel.com>
Link: https://patch.msgid.link/20251211010249.1647839-20-niranjana.vishwanathapura@intel.com
parent 7319c2ce

drivers/gpu/drm/xe/xe_debugfs.c

+2 −0
Original line number Diff line number Diff line
@@ -93,6 +93,8 @@ static int info(struct seq_file *m, void *data) 
			   xe_force_wake_ref(gt_to_fw(gt), XE_FW_GT));

		drm_printf(&p, "gt%d engine_mask 0x%llx\n", id,

			   gt->info.engine_mask);

		drm_printf(&p, "gt%d multi_queue_engine_class_mask 0x%x\n", id,

			   gt->info.multi_queue_engine_class_mask);

	}



	return 0;

drivers/gpu/drm/xe/xe_gt_types.h

+5 −0
Original line number Diff line number Diff line
@@ -140,6 +140,11 @@ struct xe_gt { 
		u64 engine_mask;

		/** @info.gmdid: raw GMD_ID value from hardware */

		u32 gmdid;

		/**

		 * @multi_queue_engine_class_mask: Bitmask of engine classes with

		 * multi queue support enabled.

		 */

		u16 multi_queue_engine_class_mask;

		/** @info.id: Unique ID of this GT within the PCI Device */

		u8 id;

		/** @info.has_indirect_ring_state: GT has indirect ring state support */

drivers/gpu/drm/xe/xe_pci.c

+1 −0
Original line number Diff line number Diff line
@@ -764,6 +764,7 @@ static struct xe_gt *alloc_primary_gt(struct xe_tile *tile, 
	gt->info.type = XE_GT_TYPE_MAIN;

	gt->info.id = tile->id * xe->info.max_gt_per_tile;

	gt->info.has_indirect_ring_state = graphics_desc->has_indirect_ring_state;

	gt->info.multi_queue_engine_class_mask = graphics_desc->multi_queue_engine_class_mask;

	gt->info.engine_mask = graphics_desc->hw_engine_mask;



	/*

drivers/gpu/drm/xe/xe_pci_types.h

+1 −0
Original line number Diff line number Diff line
@@ -60,6 +60,7 @@ struct xe_device_desc { 


struct xe_graphics_desc {

	u64 hw_engine_mask;	/* hardware engines provided by graphics IP */

	u16 multi_queue_engine_class_mask; /* bitmask of engine classes which support multi queue */



	u8 has_asid:1;

	u8 has_atomic_enable_pte_bit:1;