Commit ee7be8f3 authored by Alvin Lee's avatar Alvin Lee Committed by Alex Deucher
Browse files

drm/amd/display: Limit DCN32 8 channel or less parts to DPM1 for FPO 



- Due to hardware related QoS issues, we need to limit certain
  SKUs with less memory channels to DPM1 and above.
- At DPM0 + workload running, the urgent return latency can
  exceed 15us (the expected maximum is 4us) which results in underflow

Cc: stable@vger.kernel.org
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: default avatarSaaem Rizvi <SyedSaaem.Rizvi@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8f3589bb

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c

+2 −0
Original line number Diff line number Diff line
@@ -1888,6 +1888,8 @@ bool dcn32_validate_bandwidth(struct dc *dc, 


	dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);



	dcn32_override_min_req_memclk(dc, context);



	BW_VAL_TRACE_END_WATERMARKS();



	goto validate_out;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

+15 −0
Original line number Diff line number Diff line
@@ -2887,3 +2887,18 @@ void dcn32_set_clock_limits(const struct _vcs_dpi_soc_bounding_box_st *soc_bb) 
	dc_assert_fp_enabled();

	dcn3_2_soc.clock_limits[0].dcfclk_mhz = 1200.0;

}



void dcn32_override_min_req_memclk(struct dc *dc, struct dc_state *context)

{

	// WA: restrict FPO and SubVP to use first non-strobe mode (DCN32 BW issue)

	if ((context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dcn32_subvp_in_use(dc, context)) &&

			dc->dml.soc.num_chans <= 8) {

		int num_mclk_levels = dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels;



		if (context->bw_ctx.dml.vba.DRAMSpeed <= dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 16 &&

				num_mclk_levels > 1) {

			context->bw_ctx.dml.vba.DRAMSpeed = dc->clk_mgr->bw_params->clk_table.entries[1].memclk_mhz * 16;

			context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;

		}

	}

}

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

+2 −0
Original line number Diff line number Diff line
@@ -80,6 +80,8 @@ void dcn32_assign_fpo_vactive_candidate(struct dc *dc, const struct dc_state *co 


bool dcn32_find_vactive_pipe(struct dc *dc, const struct dc_state *context, uint32_t vactive_margin_req);



void dcn32_override_min_req_memclk(struct dc *dc, struct dc_state *context);



void dcn32_set_clock_limits(const struct _vcs_dpi_soc_bounding_box_st *soc_bb);



#endif