Commit ef8bfb00 authored by Peter Griffin's avatar Peter Griffin Committed by Martin K. Petersen
Browse files

scsi: ufs: exynos: Enable write line unique transactions on gs101 



Currently just AXIDMA_RWDATA_BURST_LEN[3:0] field is set to 8 in
exynos_ufs_post_link() function.

To enable WLU transaction additionally we need to set Write Line Unique
enable [31], Write Line Unique Burst Length [30:27] and
AXIDMA_RWDATA_BURST_LEN[3:0].

To support WLU transaction on gs101, both burst length fields need to be
0x3. As all other SoCs expect the current value we update this in the
gs101_ufs_post_link() specific hook.

Signed-off-by: default avatarPeter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20241031150033.3440894-11-peter.griffin@linaro.org


Reviewed-by: default avatarTudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
parent 9cc4a4a5

drivers/ufs/host/ufs-exynos.c

+8 −0
Original line number Diff line number Diff line
@@ -48,6 +48,8 @@ 
#define HCI_UNIPRO_APB_CLK_CTRL	0x68

#define UNIPRO_APB_CLK(v, x)	(((v) & ~0xF) | ((x) & 0xF))

#define HCI_AXIDMA_RWDATA_BURST_LEN	0x6C

#define WLU_EN			BIT(31)

#define WLU_BURST_LEN(x)	((x) << 27 | ((x) & 0xF))

#define HCI_GPIO_OUT		0x70

#define HCI_ERR_EN_PA_LAYER	0x78

#define HCI_ERR_EN_DL_LAYER	0x7C
@@ -1922,6 +1924,12 @@ static int gs101_ufs_post_link(struct exynos_ufs *ufs) 
{

	struct ufs_hba *hba = ufs->hba;



	/*

	 * Enable Write Line Unique. This field has to be 0x3

	 * to support Write Line Unique transaction on gs101.

	 */

	hci_writel(ufs, WLU_EN | WLU_BURST_LEN(3), HCI_AXIDMA_RWDATA_BURST_LEN);



	exynos_ufs_enable_dbg_mode(hba);

	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_SAVECONFIGTIME), 0x3e8);

	exynos_ufs_disable_dbg_mode(hba);