Commit effee878 authored by Dmytro Laktyushkin's avatar Dmytro Laktyushkin Committed by Alex Deucher
Browse files

drm/amd/display: fix odm k2 div calculation 



Correct setting is div by 2 for odm. Seamless odm transitions
are enabled with enable_dp_dig_pixel_rate_div_policy debug flag.

Fixes: a2c7356f ("drm/amd/display: fix pixel rate update sequence")
Reviewed-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: default avatarHamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: default avatarDmytro Laktyushkin <dmytro.laktyushkin@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 0250a714

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c

+7 −2
Original line number Diff line number Diff line
@@ -337,13 +337,14 @@ void dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable) 
		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);

}



void dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div)

unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div)

{

	struct dc_stream_state *stream = pipe_ctx->stream;

	unsigned int odm_combine_factor = 0;

	bool two_pix_per_container = false;



	two_pix_per_container = optc2_is_two_pixels_per_containter(&stream->timing);

	get_odm_config(pipe_ctx, NULL);

	odm_combine_factor = get_odm_config(pipe_ctx, NULL);



	if (stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

		*k1_div = PIXEL_RATE_DIV_BY_1;
@@ -361,11 +362,15 @@ void dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int 
		} else {

			*k1_div = PIXEL_RATE_DIV_BY_1;

			*k2_div = PIXEL_RATE_DIV_BY_4;

			if (odm_combine_factor == 2)

				*k2_div = PIXEL_RATE_DIV_BY_2;

		}

	}



	if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA))

		ASSERT(false);



	return odm_combine_factor;

}



void dcn314_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h

+1 −1
Original line number Diff line number Diff line
@@ -37,7 +37,7 @@ void dcn314_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool po 


void dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable);



void dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div);

unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div);



void dcn314_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c

+6 −2
Original line number Diff line number Diff line
@@ -1141,9 +1141,10 @@ void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx * 
	}

}



void dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div)

unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div)

{

	struct dc_stream_state *stream = pipe_ctx->stream;

	unsigned int odm_combine_factor = 0;

	bool two_pix_per_container = false;



	// For phantom pipes, use the same programming as the main pipes
@@ -1151,6 +1152,7 @@ void dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int * 
		stream = pipe_ctx->stream->mall_stream_config.paired_stream;

	}

	two_pix_per_container = optc2_is_two_pixels_per_containter(&stream->timing);

	odm_combine_factor = get_odm_config(pipe_ctx, NULL);



	if (stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

		*k1_div = PIXEL_RATE_DIV_BY_1;
@@ -1168,13 +1170,15 @@ void dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int * 
		} else {

			*k1_div = PIXEL_RATE_DIV_BY_1;

			*k2_div = PIXEL_RATE_DIV_BY_4;

			if (dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx))

			if ((odm_combine_factor == 2) || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx))

				*k2_div = PIXEL_RATE_DIV_BY_2;

		}

	}



	if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA))

		ASSERT(false);



	return odm_combine_factor;

}



void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h

+1 −1
Original line number Diff line number Diff line
@@ -71,7 +71,7 @@ void dcn32_update_force_pstate(struct dc *dc, struct dc_state *context); 


void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);



void dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div);

unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div);



void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h

+1 −1
Original line number Diff line number Diff line
@@ -156,7 +156,7 @@ struct hwseq_private_funcs { 
	void (*program_mall_pipe_config)(struct dc *dc, struct dc_state *context);

	void (*update_force_pstate)(struct dc *dc, struct dc_state *context);

	void (*update_mall_sel)(struct dc *dc, struct dc_state *context);

	void (*calculate_dccg_k1_k2_values)(struct pipe_ctx *pipe_ctx,

	unsigned int (*calculate_dccg_k1_k2_values)(struct pipe_ctx *pipe_ctx,

			unsigned int *k1_div,

			unsigned int *k2_div);

	void (*set_pixels_per_cycle)(struct pipe_ctx *pipe_ctx);