Commit f01ee019 authored by Fangzhi Zuo's avatar Fangzhi Zuo Committed by Alex Deucher
Browse files

drm/amd/display: Add DP 2.0 SST DC Support 



1. Retrieve 128/132b link cap.
2. 128/132b link training and payload allocation.
3. UHBR10 link rate support.

[squash in warning fixes - Alex]

Signed-off-by: default avatarFangzhi Zuo <Jerry.Zuo@amd.com>
Reviewed-by: default avatarNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5a2730fc

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

+8 −0
Original line number Diff line number Diff line
@@ -751,3 +751,11 @@ void dm_helpers_mst_enable_stream_features(const struct dc_stream_state *stream) 
					 &new_downspread.raw,

					 sizeof(new_downspread));

}



#if defined(CONFIG_DRM_AMD_DC_DCN)

void dm_set_phyd32clk(struct dc_context *ctx, int freq_khz)

{

       // FPGA programming for this clock in diags framework that

       // needs to go through dm layer, therefore leave dummy interace here

}

#endif
 
 No newline at end of file

drivers/gpu/drm/amd/display/dc/core/dc.c

+18 −0
Original line number Diff line number Diff line
@@ -255,6 +255,24 @@ static bool create_links( 
			goto failed_alloc;

		}



#if defined(CONFIG_DRM_AMD_DC_DCN)

		if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) &&

				dc->caps.dp_hpo &&

				link->dc->res_pool->res_cap->num_hpo_dp_link_encoder > 0) {

			/* FPGA case - Allocate HPO DP link encoder */

			if (i < link->dc->res_pool->res_cap->num_hpo_dp_link_encoder) {

				link->hpo_dp_link_enc = link->dc->res_pool->hpo_dp_link_enc[i];



				if (link->hpo_dp_link_enc == NULL) {

					BREAK_TO_DEBUGGER();

					goto failed_alloc;

				}

				link->hpo_dp_link_enc->hpd_source = link->link_enc->hpd_source;

				link->hpo_dp_link_enc->transmitter = link->link_enc->transmitter;

			}

		}

#endif



		link->link_status.dpcd_caps = &link->dpcd_caps;



		enc_init.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/core/dc_link.c

+464 −4

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drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

+1156 −7

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drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c

+299 −16

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