Unverified Commit f060fee2 authored by Rob Herring (Arm)'s avatar Rob Herring (Arm) Committed by Arnd Bergmann
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arm64: dts: lg: Add missing PL011 "uartclk" 



The PL011 IP has 2 clock inputs for UART core/baud and APB bus. The
LG131x SoCs are missing the core "uartclk". In this case, the Linux
driver uses single clock for both clock inputs. Let's assume that's how
the h/w is wired and make the DT reflect that.

Signed-off-by: default avatarRob Herring (Arm) <robh@kernel.org>
Acked-by: default avatarChanho Min <chanho.min@lge.com>
Link: https://lore.kernel.org/r/20250609-dt-lg-fixes-v1-2-e210e797c2d7@kernel.org


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent caec3157

arch/arm64/boot/dts/lg/lg131x.dtsi

+6 −6
Original line number Diff line number Diff line
@@ -128,24 +128,24 @@ uart0: serial@fe000000 { 
			compatible = "arm,pl011", "arm,primecell";

			reg = <0x0 0xfe000000 0x1000>;

			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clk_bus>;

			clock-names = "apb_pclk";

			clocks = <&clk_bus>, <&clk_bus>;

			clock-names = "uartclk", "apb_pclk";

			status = "disabled";

		};

		uart1: serial@fe100000 {

			compatible = "arm,pl011", "arm,primecell";

			reg = <0x0 0xfe100000 0x1000>;

			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clk_bus>;

			clock-names = "apb_pclk";

			clocks = <&clk_bus>, <&clk_bus>;

			clock-names = "uartclk", "apb_pclk";

			status = "disabled";

		};

		uart2: serial@fe200000 {

			compatible = "arm,pl011", "arm,primecell";

			reg = <0x0 0xfe200000 0x1000>;

			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clk_bus>;

			clock-names = "apb_pclk";

			clocks = <&clk_bus>, <&clk_bus>;

			clock-names = "uartclk", "apb_pclk";

			status = "disabled";

		};

		spi0: spi@fe800000 {