Commit f0cc697f authored by Will Deacon's avatar Will Deacon
Browse files

Merge branch 'for-next/errata' into for-next/core 

* for-next/errata:
  arm64: errata: Add workaround for Arm errata 3194386 and 3312417
  arm64: cputype: Add Neoverse-V3 definitions
  arm64: cputype: Add Cortex-X4 definitions
  arm64: barrier: Restore spec_bar() macro
parents 54e1a2aa 7187bb7d

Documentation/arch/arm64/silicon-errata.rst

+4 −0
Original line number Diff line number Diff line
@@ -140,6 +140,8 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-X2       | #2224489        | ARM64_ERRATUM_2224489       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-X4       | #3194386        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N1     | #1188873,1418040| ARM64_ERRATUM_1418040       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N1     | #1349291        | N/A                         |
@@ -156,6 +158,8 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-V1     | #1619801        | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-V3     | #3312417        | ARM64_ERRATUM_3312417       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | MMU-500         | #841119,826419  | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | MMU-600         | #1076982,1209401| N/A                         |

arch/arm64/Kconfig

+42 −0
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@@ -1066,6 +1066,48 @@ config ARM64_ERRATUM_3117295 


	  If unsure, say Y.



config ARM64_WORKAROUND_SPECULATIVE_SSBS

	bool



config ARM64_ERRATUM_3194386

	bool "Cortex-X4: 3194386: workaround for MSR SSBS not self-synchronizing"

	select ARM64_WORKAROUND_SPECULATIVE_SSBS

	default y

	help

	  This option adds the workaround for ARM Cortex-X4 erratum 3194386.



	  On affected cores "MSR SSBS, #0" instructions may not affect

	  subsequent speculative instructions, which may permit unexepected

	  speculative store bypassing.



	  Work around this problem by placing a speculation barrier after

	  kernel changes to SSBS. The presence of the SSBS special-purpose

	  register is hidden from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such

	  that userspace will use the PR_SPEC_STORE_BYPASS prctl to change

	  SSBS.



	  If unsure, say Y.



config ARM64_ERRATUM_3312417

	bool "Neoverse-V3: 3312417: workaround for MSR SSBS not self-synchronizing"

	select ARM64_WORKAROUND_SPECULATIVE_SSBS

	default y

	help

	  This option adds the workaround for ARM Neoverse-V3 erratum 3312417.



	  On affected cores "MSR SSBS, #0" instructions may not affect

	  subsequent speculative instructions, which may permit unexepected

	  speculative store bypassing.



	  Work around this problem by placing a speculation barrier after

	  kernel changes to SSBS. The presence of the SSBS special-purpose

	  register is hidden from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such

	  that userspace will use the PR_SPEC_STORE_BYPASS prctl to change

	  SSBS.



	  If unsure, say Y.





config CAVIUM_ERRATUM_22375

	bool "Cavium erratum 22375, 24313"

	default y

arch/arm64/include/asm/barrier.h

+4 −0
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@@ -40,6 +40,10 @@ 
 */

#define dgh()		asm volatile("hint #6" : : : "memory")



#define spec_bar()	asm volatile(ALTERNATIVE("dsb nsh\nisb\n",		\

						 SB_BARRIER_INSN"nop\n",	\

						 ARM64_HAS_SB))



#ifdef CONFIG_ARM64_PSEUDO_NMI

#define pmr_sync()						\

	do {							\

arch/arm64/include/asm/cpucaps.h

+2 −0
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@@ -58,6 +58,8 @@ cpucap_is_possible(const unsigned int cap) 
		return IS_ENABLED(CONFIG_NVIDIA_CARMEL_CNP_ERRATUM);

	case ARM64_WORKAROUND_REPEAT_TLBI:

		return IS_ENABLED(CONFIG_ARM64_WORKAROUND_REPEAT_TLBI);

	case ARM64_WORKAROUND_SPECULATIVE_SSBS:

		return IS_ENABLED(CONFIG_ARM64_WORKAROUND_SPECULATIVE_SSBS);

	}



	return true;

arch/arm64/include/asm/cputype.h

+4 −0
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@@ -87,6 +87,8 @@ 
#define ARM_CPU_PART_NEOVERSE_N2	0xD49

#define ARM_CPU_PART_CORTEX_A78C	0xD4B

#define ARM_CPU_PART_NEOVERSE_V2	0xD4F

#define ARM_CPU_PART_CORTEX_X4		0xD82

#define ARM_CPU_PART_NEOVERSE_V3	0xD84



#define APM_CPU_PART_XGENE		0x000

#define APM_CPU_VAR_POTENZA		0x00
@@ -161,6 +163,8 @@ 
#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)

#define MIDR_CORTEX_A78C	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C)

#define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2)

#define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4)

#define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)

#define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)

#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)

#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)