Commit f0ccd2d8 authored by Michal Wajdeczko's avatar Michal Wajdeczko
Browse files

drm/xe/vf: Don't touch GuC irq registers if using memory irqs 



On platforms where VFs are using memory based interrupts, we
missed invalid access to no longer existing interrupt registers,
as we keep them marked with XE_REG_OPTION_VF. To fix that just
either setup memirq vectors in GuC or enable legacy interrupts.

Fixes: aef4eb7c ("drm/xe/vf: Setup memory based interrupts in GuC")
Signed-off-by: default avatarMichal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240617154736.685-1-michal.wajdeczko@intel.com
parent 0e6745de

drivers/gpu/drm/xe/xe_guc.c

+2 −2
Original line number Diff line number Diff line
@@ -854,8 +854,6 @@ int xe_guc_enable_communication(struct xe_guc *guc) 
	struct xe_device *xe = guc_to_xe(guc);

	int err;



	guc_enable_irq(guc);



	if (IS_SRIOV_VF(xe) && xe_device_has_memirq(xe)) {

		struct xe_gt *gt = guc_to_gt(guc);

		struct xe_tile *tile = gt_to_tile(gt);
@@ -863,6 +861,8 @@ int xe_guc_enable_communication(struct xe_guc *guc) 
		err = xe_memirq_init_guc(&tile->sriov.vf.memirq, guc);

		if (err)

			return err;

	} else {

		guc_enable_irq(guc);

	}



	xe_mmio_rmw32(guc_to_gt(guc), PMINTRMSK,