Unverified Commit f0fd2482 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-scmi', 'clk-qcom' and 'clk-broadcom' into clk-next 

* clk-scmi:
  clk: scmi: Add duty cycle ops only when duty cycle is supported

* clk-qcom: (27 commits)
  clk: qcom: gcc-sc8280xp: drop obsolete PCIe GDSC comment
  clk: qcom: tcsrcc-x1e80100: Set the bi_tcxo as parent to eDP refclk
  clk: qcom: dispcc-glymur: Constify 'struct qcom_cc_desc'
  clk: qcom: gcc: Add support for Global Clock controller found on MSM8937
  dt-bindings: clock: qcom: Add MSM8937 Global Clock Controller
  clk: qcom: Select the intended config in QCS_DISPCC_615
  clk: qcom: common: Fix NULL vs IS_ERR() check in qcom_cc_icc_register()
  clk: qcom: alpha-pll: convert from round_rate() to determine_rate()
  clk: qcom: milos: Constify 'struct qcom_cc_desc'
  clk: qcom: gcc: Add support for Global Clock Controller
  dt-bindings: clock: qcom: document the Glymur Global Clock Controller
  clk: qcom: clk-alpha-pll: Add support for Taycan EKO_T PLL
  clk: qcom: rpmh: Add support for Glymur rpmh clocks
  clk: qcom: Add TCSR clock driver for Glymur SoC
  dt-bindings: clock: qcom: Document the Glymur SoC TCSR Clock Controller
  dt-bindings: clock: qcom-rpmhcc: Add support for Glymur SoCs
  clk: qcom: dispcc-glymur: Add support for Display Clock Controller
  dt-bindings: clock: Add DISPCC and reset controller for GLYMUR SoC
  clk: qcom: gcc-sdm660: Add missing LPASS/CDSP vote clocks
  dt-bindings: clock: gcc-sdm660: Add LPASS/CDSP vote clocks/GDSCs
  ...

* clk-broadcom:
  clk: bcm: rpi: Maximize V3D clock
  clk: bcm: rpi: Turn firmware clock on/off when preparing/unpreparing
  clk: bcm: rpi: Add missing logs if firmware fails
parents c1e102f3 18db1ff2 575e9a62 6526402b

Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml

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@@ -9,16 +9,21 @@ title: Qualcomm Global Clock & Reset Controller on MSM8953 
maintainers:

  - Adam Skladowski <a_skl39@protonmail.com>

  - Sireesh Kodali <sireeshkodali@protonmail.com>

  - Barnabas Czeman <barnabas.czeman@mainlining.org>



description: |

  Qualcomm global clock control module provides the clocks, resets and power

  domains on MSM8953.

  domains on MSM8937 or MSM8953.



  See also: include/dt-bindings/clock/qcom,gcc-msm8953.h

  See also::

    include/dt-bindings/clock/qcom,gcc-msm8917.h

    include/dt-bindings/clock/qcom,gcc-msm8953.h



properties:

  compatible:

    const: qcom,gcc-msm8953

    enum:

      - qcom,gcc-msm8937

      - qcom,gcc-msm8953



  clocks:

    items:

Documentation/devicetree/bindings/clock/qcom,glymur-dispcc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,glymur-dispcc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Display Clock & Reset Controller on GLYMUR



maintainers:

  - Taniya Das <taniya.das@oss.qualcomm.com>



description: |

  Qualcomm display clock control module which supports the clocks, resets and

  power domains for the MDSS instances on GLYMUR SoC.



  See also:

    include/dt-bindings/clock/qcom,dispcc-glymur.h



properties:

  compatible:

    enum:

      - qcom,glymur-dispcc



  clocks:

    items:

      - description: Board CXO clock

      - description: Board sleep clock

      - description: DisplayPort 0 link clock

      - description: DisplayPort 0 VCO div clock

      - description: DisplayPort 1 link clock

      - description: DisplayPort 1 VCO div clock

      - description: DisplayPort 2 link clock

      - description: DisplayPort 2 VCO div clock

      - description: DisplayPort 3 link clock

      - description: DisplayPort 3 VCO div clock

      - description: DSI 0 PLL byte clock

      - description: DSI 0 PLL DSI clock

      - description: DSI 1 PLL byte clock

      - description: DSI 1 PLL DSI clock

      - description: Standalone PHY 0 PLL link clock

      - description: Standalone PHY 0 VCO div clock

      - description: Standalone PHY 1 PLL link clock

      - description: Standalone PHY 1 VCO div clock



  power-domains:

    description:

      A phandle and PM domain specifier for the MMCX power domain.

    maxItems: 1



  required-opps:

    description:

      A phandle to an OPP node describing required MMCX performance point.

    maxItems: 1



required:

  - compatible

  - clocks

  - power-domains

  - '#power-domain-cells'



allOf:

  - $ref: qcom,gcc.yaml#



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,rpmh.h>

    #include <dt-bindings/power/qcom,rpmhpd.h>



    clock-controller@af00000 {

      compatible = "qcom,glymur-dispcc";

      reg = <0x0af00000 0x20000>;

      clocks = <&rpmhcc RPMH_CXO_CLK>,

               <&sleep_clk>,

               <&mdss_dp_phy0 0>,

               <&mdss_dp_phy0 1>,

               <&mdss_dp_phy1 0>,

               <&mdss_dp_phy1 1>,

               <&mdss_dp_phy2 0>,

               <&mdss_dp_phy2 1>,

               <&mdss_dp_phy3 0>,

               <&mdss_dp_phy3 1>,

               <&mdss_dsi0_phy 0>,

               <&mdss_dsi0_phy 1>,

               <&mdss_dsi1_phy 0>,

               <&mdss_dsi1_phy 1>,

               <&mdss_phy0_link 0>,

               <&mdss_phy0_vco_div 0>,

               <&mdss_phy1_link 1>,

               <&mdss_phy1_vco_div 1>;

      power-domains = <&rpmhpd RPMHPD_MMCX>;

      required-opps = <&rpmhpd_opp_low_svs>;

      #clock-cells = <1>;

      #reset-cells = <1>;

      #power-domain-cells = <1>;

    };

...

Documentation/devicetree/bindings/clock/qcom,glymur-gcc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,glymur-gcc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Global Clock & Reset Controller on Glymur SoC



maintainers:

  - Taniya Das <taniya.das@oss.qualcomm.com>



description: |

  Qualcomm global clock control module provides the clocks, resets and power

  domains on Glymur SoC.



  See also: include/dt-bindings/clock/qcom,glymur-gcc.h



properties:

  compatible:

    const: qcom,glymur-gcc



  clocks:

    items:

      - description: Board XO source

      - description: Board XO_A source

      - description: Sleep clock source

      - description: USB 0 Phy DP0 GMUX clock source

      - description: USB 0 Phy DP1 GMUX clock source

      - description: USB 0 Phy PCIE PIPEGMUX clock source

      - description: USB 0 Phy PIPEGMUX clock source

      - description: USB 0 Phy SYS PCIE PIPEGMUX clock source

      - description: USB 1 Phy DP0 GMUX 2 clock source

      - description: USB 1 Phy DP1 GMUX 2 clock source

      - description: USB 1 Phy PCIE PIPEGMUX clock source

      - description: USB 1 Phy PIPEGMUX clock source

      - description: USB 1 Phy SYS PCIE PIPEGMUX clock source

      - description: USB 2 Phy DP0 GMUX 2 clock source

      - description: USB 2 Phy DP1 GMUX 2 clock source

      - description: USB 2 Phy PCIE PIPEGMUX clock source

      - description: USB 2 Phy PIPEGMUX clock source

      - description: USB 2 Phy SYS PCIE PIPEGMUX clock source

      - description: PCIe 3a pipe clock

      - description: PCIe 3b pipe clock

      - description: PCIe 4 pipe clock

      - description: PCIe 5 pipe clock

      - description: PCIe 6 pipe clock

      - description: QUSB4 0 PHY RX 0 clock source

      - description: QUSB4 0 PHY RX 1 clock source

      - description: QUSB4 1 PHY RX 0 clock source

      - description: QUSB4 1 PHY RX 1 clock source

      - description: QUSB4 2 PHY RX 0 clock source

      - description: QUSB4 2 PHY RX 1 clock source

      - description: UFS PHY RX Symbol 0 clock source

      - description: UFS PHY RX Symbol 1 clock source

      - description: UFS PHY TX Symbol 0 clock source

      - description: USB3 PHY 0 pipe clock source

      - description: USB3 PHY 1 pipe clock source

      - description: USB3 PHY 2 pipe clock source

      - description: USB3 UNI PHY pipe 0 clock source

      - description: USB3 UNI PHY pipe 1 clock source

      - description: USB4 PHY 0 pcie pipe clock source

      - description: USB4 PHY 0 Max pipe clock source

      - description: USB4 PHY 1 pcie pipe clock source

      - description: USB4 PHY 1 Max pipe clock source

      - description: USB4 PHY 2 pcie pipe clock source

      - description: USB4 PHY 2 Max pipe clock source



required:

  - compatible

  - clocks

  - '#power-domain-cells'



allOf:

  - $ref: qcom,gcc.yaml#



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,rpmh.h>

    clock-controller@100000 {

      compatible = "qcom,glymur-gcc";

      reg = <0x100000 0x1f9000>;

      clocks = <&rpmhcc RPMH_CXO_CLK>,

               <&rpmhcc RPMH_CXO_CLK_A>,

               <&sleep_clk>,

               <&usb_0_phy_dp0_gmux>,

               <&usb_0_phy_dp1_gmux>,

               <&usb_0_phy_pcie_pipegmux>,

               <&usb_0_phy_pipegmux>,

               <&usb_0_phy_sys_pcie_pipegmux>,

               <&usb_1_phy_dp0_gmux_2>,

               <&usb_1_phy_dp1_gmux_2>,

               <&usb_1_phy_pcie_pipegmux>,

               <&usb_1_phy_pipegmux>,

               <&usb_1_phy_sys_pcie_pipegmux>,

               <&usb_2_phy_dp0_gmux 2>,

               <&usb_2_phy_dp1_gmux 2>,

               <&usb_2_phy_pcie_pipegmux>,

               <&usb_2_phy_pipegmux>,

               <&usb_2_phy_sys_pcie_pipegmux>,

               <&pcie_3a_pipe>, <&pcie_3b_pipe>,

               <&pcie_4_pipe>, <&pcie_5_pipe>,

               <&pcie_6_pipe>,

               <&qusb4_0_phy_rx_0>, <&qusb4_0_phy_rx_1>,

               <&qusb4_1_phy_rx_0>, <&qusb4_1_phy_rx_1>,

               <&qusb4_2_phy_rx_0>, <&qusb4_2_phy_rx_1>,

               <&ufs_phy_rx_symbol_0>, <&ufs_phy_rx_symbol_1>,

               <&ufs_phy_tx_symbol_0>,

               <&usb3_phy_0_pipe>, <&usb3_phy_1_pipe>,

               <&usb3_phy_2_pipe>,

               <&usb3_uni_phy_pipe_0>, <&usb3_uni_phy_pipe_1>,

               <&usb4_phy_0_pcie_pipe>, <&usb4_phy_0_max_pipe>,

               <&usb4_phy_1_pcie_pipe>, <&usb4_phy_1_max_pipe>,

               <&usb4_phy_2_pcie_pipe>, <&usb4_phy_2_max_pipe>;

      #clock-cells = <1>;

      #reset-cells = <1>;

      #power-domain-cells = <1>;

    };



...

Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,ipq5424-apss-clk.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm APSS IPQ5424 Clock Controller



maintainers:

  - Varadarajan Narayanan <quic_varada@quicinc.com>



description:

  The CPU core in ipq5424 is clocked by a huayra PLL with RCG support.

  The RCG and PLL have a separate register space from the GCC.



properties:

  compatible:

    enum:

      - qcom,ipq5424-apss-clk



  reg:

    maxItems: 1



  clocks:

    items:

      - description: Reference to the XO clock.

      - description: Reference to the GPLL0 clock.



  '#clock-cells':

    const: 1



  '#interconnect-cells':

    const: 1



required:

  - compatible

  - reg

  - clocks

  - '#clock-cells'

  - '#interconnect-cells'



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,ipq5424-gcc.h>



    apss_clk: clock-controller@fa80000 {

      compatible = "qcom,ipq5424-apss-clk";

      reg = <0x0fa80000 0x20000>;

      clocks = <&xo_board>,

               <&gcc GPLL0>;

      #clock-cells = <1>;

      #interconnect-cells = <1>;

    };

Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml

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@@ -17,6 +17,7 @@ description: | 
properties:

  compatible:

    enum:

      - qcom,glymur-rpmh-clk

      - qcom,milos-rpmh-clk

      - qcom,qcs615-rpmh-clk

      - qcom,qdu1000-rpmh-clk