Commit f15de193 authored by Michal Wajdeczko's avatar Michal Wajdeczko Committed by Rodrigo Vivi
Browse files

drm/xe: Add XE_BO_NEEDS_UC flag to force UC mode instead WB 



When we map BO in GGTT, then by default we are using PAT index
that corresponds to XE_CACHE_WB but ppcoming feature will require
use of the PAT index of the XE_CACHE_UC.  Define new BO flag that
could be used during BO creation to force alternate caching.

Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20231214185955.1791-7-michal.wajdeczko@intel.com


Signed-off-by: default avatarMichal Wajdeczko <michal.wajdeczko@intel.com>
parent 35c933f6

drivers/gpu/drm/xe/xe_bo.h

+1 −0
Original line number Diff line number Diff line
@@ -44,6 +44,7 @@ 
#define XE_BO_FIXED_PLACEMENT_BIT	BIT(11)

#define XE_BO_PAGETABLE			BIT(12)

#define XE_BO_NEEDS_CPU_ACCESS		BIT(13)

#define XE_BO_NEEDS_UC			BIT(14)

/* this one is trigger internally only */

#define XE_BO_INTERNAL_TEST		BIT(30)

#define XE_BO_INTERNAL_64K		BIT(31)

drivers/gpu/drm/xe/xe_ggtt.c

+2 −1
Original line number Diff line number Diff line
@@ -334,7 +334,8 @@ int xe_ggtt_insert_special_node(struct xe_ggtt *ggtt, struct drm_mm_node *node, 


void xe_ggtt_map_bo(struct xe_ggtt *ggtt, struct xe_bo *bo)

{

	u16 pat_index = tile_to_xe(ggtt->tile)->pat.idx[XE_CACHE_WB];

	u16 cache_mode = bo->flags & XE_BO_NEEDS_UC ? XE_CACHE_NONE : XE_CACHE_WB;

	u16 pat_index = tile_to_xe(ggtt->tile)->pat.idx[cache_mode];

	u64 start = bo->ggtt_node.start;

	u64 offset, pte;