Commit f17a2293 authored by Jingyi Wang's avatar Jingyi Wang Committed by Bjorn Andersson
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arm64: dts: qcom: qcs8300: Add LLCC support for QCS8300 



Add Last Level Cache Controller node on the QCS8300 platform.

Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: default avatarJingyi Wang <quic_jingyw@quicinc.com>
Link: https://lore.kernel.org/r/20241031-qcs8300_llcc-v3-3-bb56952cb83b@quicinc.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 09d8a3ef

arch/arm64/boot/dts/qcom/qcs8300.dtsi

+15 −0
Original line number Diff line number Diff line
@@ -2684,6 +2684,21 @@ gem_noc: interconnect@9100000 { 
			qcom,bcm-voters = <&apps_bcm_voter>;

		};



		llcc: system-cache-controller@9200000 {

			compatible = "qcom,qcs8300-llcc";

			reg = <0x0 0x09200000 0x0 0x80000>,

			      <0x0 0x09300000 0x0 0x80000>,

			      <0x0 0x09400000 0x0 0x80000>,

			      <0x0 0x09500000 0x0 0x80000>,

			      <0x0 0x09a00000 0x0 0x80000>;

			reg-names = "llcc0_base",

				    "llcc1_base",

				    "llcc2_base",

				    "llcc3_base",

				    "llcc_broadcast_base";

			interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;

		};



		pdc: interrupt-controller@b220000 {

			compatible = "qcom,qcs8300-pdc", "qcom,pdc";

			reg = <0x0 0xb220000 0x0 0x30000>,