Commit f22be5c1 authored by Neil Armstrong's avatar Neil Armstrong Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: sm8650: add missing cpu-cfg interconnect path in the mdss node 



The bindings requires the mdp0-mem and the cpu-cfg interconnect path,
add the missing cpu-cfg path to fix the dtbs check error and also to ensure
that MDSS has enough bandwidth to let HLOS write config registers.

Fixes: 9fa33cbc ("arm64: dts: qcom: sm8650: correct MDSS interconnects")
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250227-topic-sm8x50-mdss-interconnect-bindings-fix-v5-2-bf6233c6ebe5@linaro.org


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 327d489d

arch/arm64/boot/dts/qcom/sm8650.dtsi

+5 −2
Original line number Diff line number Diff line
@@ -4930,8 +4930,11 @@ mdss: display-subsystem@ae00000 { 
			resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;



			interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS

					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;

			interconnect-names = "mdp0-mem";

					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,

					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY

					 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;

			interconnect-names = "mdp0-mem",

					     "cpu-cfg";



			power-domains = <&dispcc MDSS_GDSC>;