Commit f2e6f002 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-6.14-2025-02-05' of... 

Merge tag 'amd-drm-fixes-6.14-2025-02-05' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes

amd-drm-fixes-6.14-2025-02-05:

amdgpu:
- Add BO metadata flag for DCC
- Fix potential out of bounds access in display
- Seamless boot fix
- CONFIG_FRAME_WARN fix
- PSR1 fix

UAPI:
- Add new tiling flag for DCC write compress disable
  Proposed userspace: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33255



Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250205214910.3664690-1-alexander.deucher@amd.com
parents 2014c95a f245b400

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+2 −1
Original line number Diff line number Diff line
@@ -119,9 +119,10 @@ 
 * - 3.57.0 - Compute tunneling on GFX10+

 * - 3.58.0 - Add GFX12 DCC support

 * - 3.59.0 - Cleared VRAM

 * - 3.60.0 - Add AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE (Vulkan requirement)

 */

#define KMS_DRIVER_MAJOR	3

#define KMS_DRIVER_MINOR	59

#define KMS_DRIVER_MINOR	60

#define KMS_DRIVER_PATCHLEVEL	0



/*

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

+6 −2
Original line number Diff line number Diff line
@@ -309,7 +309,7 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, 
	mutex_lock(&adev->mman.gtt_window_lock);

	while (src_mm.remaining) {

		uint64_t from, to, cur_size, tiling_flags;

		uint32_t num_type, data_format, max_com;

		uint32_t num_type, data_format, max_com, write_compress_disable;

		struct dma_fence *next;



		/* Never copy more than 256MiB at once to avoid a timeout */
@@ -340,9 +340,13 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, 
			max_com = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_MAX_COMPRESSED_BLOCK);

			num_type = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_NUMBER_TYPE);

			data_format = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_DATA_FORMAT);

			write_compress_disable =

				AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_WRITE_COMPRESS_DISABLE);

			copy_flags |= (AMDGPU_COPY_FLAGS_SET(MAX_COMPRESSED, max_com) |

				       AMDGPU_COPY_FLAGS_SET(NUMBER_TYPE, num_type) |

				       AMDGPU_COPY_FLAGS_SET(DATA_FORMAT, data_format));

				       AMDGPU_COPY_FLAGS_SET(DATA_FORMAT, data_format) |

				       AMDGPU_COPY_FLAGS_SET(WRITE_COMPRESS_DISABLE,

							     write_compress_disable));

		}



		r = amdgpu_copy_buffer(ring, from, to, cur_size, resv,

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h

+2 −0
Original line number Diff line number Diff line
@@ -119,6 +119,8 @@ struct amdgpu_copy_mem { 
#define AMDGPU_COPY_FLAGS_NUMBER_TYPE_MASK		0x07

#define AMDGPU_COPY_FLAGS_DATA_FORMAT_SHIFT		8

#define AMDGPU_COPY_FLAGS_DATA_FORMAT_MASK		0x3f

#define AMDGPU_COPY_FLAGS_WRITE_COMPRESS_DISABLE_SHIFT	14

#define AMDGPU_COPY_FLAGS_WRITE_COMPRESS_DISABLE_MASK	0x1



#define AMDGPU_COPY_FLAGS_SET(field, value) \

	(((__u32)(value) & AMDGPU_COPY_FLAGS_##field##_MASK) << AMDGPU_COPY_FLAGS_##field##_SHIFT)

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

+3 −2
Original line number Diff line number Diff line
@@ -1741,11 +1741,12 @@ static void sdma_v7_0_emit_copy_buffer(struct amdgpu_ib *ib, 
				       uint32_t byte_count,

				       uint32_t copy_flags)

{

	uint32_t num_type, data_format, max_com;

	uint32_t num_type, data_format, max_com, write_cm;



	max_com = AMDGPU_COPY_FLAGS_GET(copy_flags, MAX_COMPRESSED);

	data_format = AMDGPU_COPY_FLAGS_GET(copy_flags, DATA_FORMAT);

	num_type = AMDGPU_COPY_FLAGS_GET(copy_flags, NUMBER_TYPE);

	write_cm = AMDGPU_COPY_FLAGS_GET(copy_flags, WRITE_COMPRESS_DISABLE) ? 2 : 1;



	ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) |

		SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
@@ -1762,7 +1763,7 @@ static void sdma_v7_0_emit_copy_buffer(struct amdgpu_ib *ib, 
	if ((copy_flags & (AMDGPU_COPY_FLAGS_READ_DECOMPRESSED | AMDGPU_COPY_FLAGS_WRITE_COMPRESSED)))

		ib->ptr[ib->length_dw++] = SDMA_DCC_DATA_FORMAT(data_format) | SDMA_DCC_NUM_TYPE(num_type) |

			((copy_flags & AMDGPU_COPY_FLAGS_READ_DECOMPRESSED) ? SDMA_DCC_READ_CM(2) : 0) |

			((copy_flags & AMDGPU_COPY_FLAGS_WRITE_COMPRESSED) ? SDMA_DCC_WRITE_CM(1) : 0) |

			((copy_flags & AMDGPU_COPY_FLAGS_WRITE_COMPRESSED) ? SDMA_DCC_WRITE_CM(write_cm) : 0) |

			SDMA_DCC_MAX_COM(max_com) | SDMA_DCC_MAX_UCOM(1);

	else

		ib->ptr[ib->length_dw++] = 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

+1 −1
Original line number Diff line number Diff line
@@ -2133,7 +2133,7 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c 


	dc_enable_stereo(dc, context, dc_streams, context->stream_count);



	if (context->stream_count > get_seamless_boot_stream_count(context) ||

	if (get_seamless_boot_stream_count(context) == 0 ||

		context->stream_count == 0) {

		/* Must wait for no flips to be pending before doing optimize bw */

		hwss_wait_for_no_pipes_pending(dc, context);