Commit f2ef3972 authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull spi updates from Mark Brown:
 "The only real core work we've got this time around is the completion
  of the transition to the new host/target naming for the core APIs,
  Kconfig still needs doing but that's a lot less invasive.

  Otherwise the big changes are the new drivers that have been added:

   - Completion of the conversion to spi_alloc_host()/_target() and
     removal of the old naming.

   - Cleanups for Rockchip drivers, these brought in a new logging
     helper in the driver core for warnings during probe.

   - Support for configuration of the word delay via spidev_test.

   - Support for AMD HID2 controllers, Apple SPI controller and Realtek
     SPI-NAND controllers"

* tag 'spi-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (58 commits)
  spi: imx: support word delay
  spi: imx: pass struct spi_transfer to prepare_transfer()
  spi: cs42l43: Add GPIO speaker id support to the bridge configuration
  spi: Delete useless checks
  spi: apple: Remove unnecessary .owner for apple_spi_driver
  spi: spidev_test: add support for word delay
  spi: apple: Add driver for Apple SPI controller
  spi: dt-bindings: apple,spi: Add binding for Apple SPI controllers
  spi: Use of_property_present() for non-boolean properties
  spi: zynqmp-gqspi: Undo runtime PM changes at driver exit time​
  spi: spi-mem: rtl-snand: Correctly handle DMA transfers
  spi: tegra210-quad: Avoid shift-out-of-bounds
  spi: axi-spi-engine: Emit trace events for spi transfers
  dt-bindings: spi: sprd,sc9860-spi: convert to YAML
  spi: Replace deprecated PCI functions
  spi: dt-bindings: samsung: Add a compatible for samsung,exynos8895-spi
  spi: spi-mem: Add Realtek SPI-NAND controller
  dt-bindings: spi: Add realtek,rtl9301-snand
  spi: make class structs const
  spi: dt-bindings: brcm,bcm2835-aux-spi: Convert to dtschema
  ...
parents 4bd37a90 26470a2e
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What:		/sys/devices/.../intel_spi_protected
Date:		Feb 2025
KernelVersion:	6.13
Contact:	Alexander Usyskin <alexander.usyskin@intel.com>
Description:	This attribute allows the userspace to check if the
		Intel SPI flash controller is write protected from the host.

What:		/sys/devices/.../intel_spi_locked
Date:		Feb 2025
KernelVersion:	6.13
Contact:	Alexander Usyskin <alexander.usyskin@intel.com>
Description:	This attribute allows the user space to check if the
		Intel SPI flash controller locks supported opcodes.

What:		/sys/devices/.../intel_spi_bios_locked
Date:		Feb 2025
KernelVersion:	6.13
Contact:	Alexander Usyskin <alexander.usyskin@intel.com>
Description:	This attribute allows the user space to check if the
		Intel SPI flash controller BIOS region is locked for writes.
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/apple,spi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Apple ARM SoC SPI controller

allOf:
  - $ref: spi-controller.yaml#

maintainers:
  - Hector Martin <marcan@marcan.st>

properties:
  compatible:
    items:
      - enum:
          - apple,t8103-spi
          - apple,t8112-spi
          - apple,t6000-spi
      - const: apple,spi

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  interrupts:
    maxItems: 1

  power-domains:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - interrupts

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/apple-aic.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    soc {
      #address-cells = <2>;
      #size-cells = <2>;

      spi@39b104000 {
        compatible = "apple,t6000-spi", "apple,spi";
        reg = <0x3 0x9b104000 0x0 0x4000>;
        interrupt-parent = <&aic>;
        interrupts = <AIC_IRQ 0 1107 IRQ_TYPE_LEVEL_HIGH>;
        #address-cells = <1>;
        #size-cells = <0>;
        clocks = <&clk>;
      };
    };
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Broadcom BCM2835 auxiliary SPI1/2 controller

The BCM2835 contains two forms of SPI master controller, one known simply as
SPI0, and the other known as the "Universal SPI Master"; part of the
auxiliary block. This binding applies to the SPI1/2 controller.

Required properties:
- compatible: Should be "brcm,bcm2835-aux-spi".
- reg: Should contain register location and length for the spi block
- interrupts: Should contain shared interrupt of the aux block
- clocks: The clock feeding the SPI controller - needs to
	  point to the auxiliary clock driver of the bcm2835,
	  as this clock will enable the output gate for the specific
	  clock.
- cs-gpios: the cs-gpios (native cs is NOT supported)
	    see also spi-bus.txt

Example:

spi1@7e215080 {
	compatible = "brcm,bcm2835-aux-spi";
	reg = <0x7e215080 0x40>;
	interrupts = <1 29>;
	clocks = <&aux_clocks BCM2835_AUX_CLOCK_SPI1>;
	#address-cells = <1>;
	#size-cells = <0>;
	cs-gpios = <&gpio 18>, <&gpio 17>, <&gpio 16>;
};

spi2@7e2150c0 {
	compatible = "brcm,bcm2835-aux-spi";
	reg = <0x7e2150c0 0x40>;
	interrupts = <1 29>;
	clocks = <&aux_clocks BCM2835_AUX_CLOCK_SPI2>;
	#address-cells = <1>;
	#size-cells = <0>;
	cs-gpios = <&gpio 43>, <&gpio 44>, <&gpio 45>;
};
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/brcm,bcm2835-aux-spi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom BCM2835 Auxiliary SPI1/2 Controller

maintainers:
  - Karan Sanghavi <karansanghvi98@gmail.com>

description:
  The BCM2835 contains two forms of SPI master controller. One is known simply
  as SPI0, and the other as the "Universal SPI Master," which is part of the
  auxiliary block. This binding applies to the SPI1 and SPI2 auxiliary
  controllers.

allOf:
  - $ref: spi-controller.yaml#

properties:
  compatible:
    enum:
      - brcm,bcm2835-aux-spi

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/bcm2835-aux.h>
    spi@7e215080 {
        compatible = "brcm,bcm2835-aux-spi";
        reg = <0x7e215080 0x40>;
        interrupts = <1 29>;
        clocks = <&aux_clocks BCM2835_AUX_CLOCK_SPI1>;
        #address-cells = <1>;
        #size-cells = <0>;
    };
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/realtek,rtl9301-snand.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: SPI-NAND Flash Controller for Realtek RTL9300 SoCs

maintainers:
  - Chris Packham <chris.packham@alliedtelesis.co.nz>

description:
  The Realtek RTL9300 SoCs have a built in SPI-NAND controller. It supports
  typical SPI-NAND page cache operations in single, dual or quad IO mode.

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - realtek,rtl9302b-snand
              - realtek,rtl9302c-snand
              - realtek,rtl9303-snand
          - const: realtek,rtl9301-snand
      - const: realtek,rtl9301-snand

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks

allOf:
  - $ref: /schemas/spi/spi-controller.yaml#

unevaluatedProperties: false

examples:
  - |
    spi@1a400 {
      compatible = "realtek,rtl9302c-snand", "realtek,rtl9301-snand";
      reg = <0x1a400 0x44>;
      interrupt-parent = <&intc>;
      interrupts = <19>;
      clocks = <&lx_clk>;
      #address-cells = <1>;
      #size-cells = <0>;

      flash@0 {
        compatible = "spi-nand";
        reg = <0>;
      };
    };
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