Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net

    -e ali_drw_27080/hif_rmw/ \

    -e ali_drw_27080/cycle/ -- sleep 10

Example usage of counting all memory read/write bandwidth by metric::

  perf stat -M ddr_read_bandwidth.all -- sleep 10

  perf stat -M ddr_write_bandwidth.all -- sleep 10

The average DRAM bandwidth can be calculated as follows:

- Read Bandwidth =  perf_hif_rd * DDRC_WIDTH * DDRC_Freq / DDRC_Cycle

``IA64_THREAD_UAC_NOPRINT`` ``prctl`` and avoid logs being flooded.

io_uring_disabled

=================

Prevents all processes from creating new io_uring instances. Enabling this

shrinks the kernel's attack surface.

= ======================================================================

0 All processes can create io_uring instances as normal. This is the

  default setting.

1 io_uring creation is disabled (io_uring_setup() will fail with

  -EPERM) for unprivileged processes not in the io_uring_group group.

  Existing io_uring instances can still be used.  See the

  documentation for io_uring_group for more information.

2 io_uring creation is disabled for all processes. io_uring_setup()

  always fails with -EPERM. Existing io_uring instances can still be

  used.

= ======================================================================

io_uring_group

==============

When io_uring_disabled is set to 1, a process must either be

privileged (CAP_SYS_ADMIN) or be in the io_uring_group group in order

to create an io_uring instance.  If io_uring_group is set to -1 (the

default), only processes with the CAP_SYS_ADMIN capability may create

io_uring instances.

kexec_load_disabled

===================

Architectures

~~~~~~~~~~~~~

Generic KASAN is supported on x86_64, arm, arm64, powerpc, riscv, s390, and

xtensa, and the tag-based KASAN modes are supported only on arm64.

Generic KASAN is supported on x86_64, arm, arm64, powerpc, riscv, s390, xtensa,

and loongarch, and the tag-based KASAN modes are supported only on arm64.

Compilers

~~~~~~~~~

# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

# Copyright (C) 2023 Renesas Electronics Corp.

%YAML 1.2

---

$id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Andestech AX45MP L2 Cache Controller

maintainers:

  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

description:

  A level-2 cache (L2C) is used to improve the system performance by providing

  a large amount of cache line entries and reasonable access delays. The L2C

  is shared between cores, and a non-inclusive non-exclusive policy is used.

select:

  properties:

    compatible:

      contains:

        enum:

          - andestech,ax45mp-cache

  required:

    - compatible

properties:

  compatible:

    items:

      - const: andestech,ax45mp-cache

      - const: cache

  reg:

    maxItems: 1

  interrupts:

    maxItems: 1

  cache-line-size:

    const: 64

  cache-level:

    const: 2

  cache-sets:

    const: 1024

  cache-size:

    enum: [131072, 262144, 524288, 1048576, 2097152]

  cache-unified: true

  next-level-cache: true

additionalProperties: false

required:

  - compatible

  - reg

  - interrupts

  - cache-line-size

  - cache-level

  - cache-sets

  - cache-size

  - cache-unified

examples:

  - |

    #include <dt-bindings/interrupt-controller/irq.h>

    cache-controller@2010000 {

        compatible = "andestech,ax45mp-cache", "cache";

        reg = <0x13400000 0x100000>;

        interrupts = <508 IRQ_TYPE_LEVEL_HIGH>;

        cache-line-size = <64>;

        cache-level = <2>;

        cache-sets = <1024>;

        cache-size = <262144>;

        cache-unified;

    };

    pattern: "^easrc@.*"

  compatible:

    const: fsl,imx8mn-easrc

    oneOf:

      - enum:

          - fsl,imx8mn-easrc

      - items:

          - enum:

              - fsl,imx8mp-easrc

          - const: fsl,imx8mn-easrc

  reg:

    maxItems: 1