Commit f34da560 authored by Jerome Brunet's avatar Jerome Brunet
Browse files

Merge branch 'v6.11/bindings' into v6.11/drivers

* v6.11/bindings:
  dt-bindings: clock: meson: a1: peripherals: support sys_pll input
  dt-bindings: clock: meson: a1: pll: introduce new syspll bindings
parents d4c83ac1 41056416
Loading
Loading
Loading
Loading
+7 −2
Original line number Diff line number Diff line
@@ -30,6 +30,8 @@ properties:
      - description: input fixed pll div7
      - description: input hifi pll
      - description: input oscillator (usually at 24MHz)
      - description: input sys pll
    minItems: 6 # sys_pll is optional

  clock-names:
    items:
@@ -39,6 +41,8 @@ properties:
      - const: fclk_div7
      - const: hifi_pll
      - const: xtal
      - const: sys_pll
    minItems: 6 # sys_pll is optional

required:
  - compatible
@@ -65,9 +69,10 @@ examples:
                     <&clkc_pll CLKID_FCLK_DIV5>,
                     <&clkc_pll CLKID_FCLK_DIV7>,
                     <&clkc_pll CLKID_HIFI_PLL>,
                     <&xtal>;
                     <&xtal>,
                     <&clkc_pll CLKID_SYS_PLL>;
            clock-names = "fclk_div2", "fclk_div3",
                          "fclk_div5", "fclk_div7",
                          "hifi_pll", "xtal";
                          "hifi_pll", "xtal", "sys_pll";
        };
    };
+7 −2
Original line number Diff line number Diff line
@@ -26,11 +26,15 @@ properties:
    items:
      - description: input fixpll_in
      - description: input hifipll_in
      - description: input syspll_in
    minItems: 2 # syspll_in is optional

  clock-names:
    items:
      - const: fixpll_in
      - const: hifipll_in
      - const: syspll_in
    minItems: 2 # syspll_in is optional

required:
  - compatible
@@ -53,7 +57,8 @@ examples:
            reg = <0 0x7c80 0 0x18c>;
            #clock-cells = <1>;
            clocks = <&clkc_periphs CLKID_FIXPLL_IN>,
                     <&clkc_periphs CLKID_HIFIPLL_IN>;
            clock-names = "fixpll_in", "hifipll_in";
                     <&clkc_periphs CLKID_HIFIPLL_IN>,
                     <&clkc_periphs CLKID_SYSPLL_IN>;
            clock-names = "fixpll_in", "hifipll_in", "syspll_in";
        };
    };
+1 −0
Original line number Diff line number Diff line
@@ -164,5 +164,6 @@
#define CLKID_DMC_SEL		151
#define CLKID_DMC_DIV		152
#define CLKID_DMC_SEL2		153
#define CLKID_SYS_PLL_DIV16	154

#endif /* __A1_PERIPHERALS_CLKC_H */
+1 −0
Original line number Diff line number Diff line
@@ -21,5 +21,6 @@
#define CLKID_FCLK_DIV5		8
#define CLKID_FCLK_DIV7		9
#define CLKID_HIFI_PLL		10
#define CLKID_SYS_PLL		11

#endif /* __A1_PLL_CLKC_H */