Commit f38f7fe4 authored by Jerome Brunet's avatar Jerome Brunet
Browse files

clk: amlogic: gxbb: drop incorrect flag on 32k clock 



gxbb_32k_clk_div sets CLK_DIVIDER_ROUND_CLOSEST in the init_data flag which
is incorrect. This is field is not where the divider flags belong.

Thankfully, CLK_DIVIDER_ROUND_CLOSEST maps to bit 4 which is an unused
clock flag, so there is no unintended consequence to this error.

Effectively, the clock has been used without CLK_DIVIDER_ROUND_CLOSEST
so far, so just drop it.

Fixes: 14c735c8 ("clk: meson-gxbb: Add EE 32K Clock for CEC")
Reviewed-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20241220-amlogic-clk-gxbb-32k-fixes-v1-1-baca56ecf2db@baylibre.com


Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
parent 8995f8f1

drivers/clk/meson/gxbb.c

+1 −1
Original line number Diff line number Diff line
@@ -1306,7 +1306,7 @@ static struct clk_regmap gxbb_32k_clk_div = { 
			&gxbb_32k_clk_sel.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,

		.flags = CLK_SET_RATE_PARENT,

	},

};