Unverified Commit f3cb045e authored by Kaustabh Chakraborty's avatar Kaustabh Chakraborty Committed by Inki Dae
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drm/exynos: exynos7_drm_decon: fix ideal_clk by converting it to Hz 



The clkdiv values are incorrect as ideal_clk is in kHz and the clock
rate of vclk is in Hz. Multiply 1000 to ideal_clk to bring it to Hz.

Signed-off-by: default avatarKaustabh Chakraborty <kauschluss@disroot.org>
Signed-off-by: default avatarInki Dae <inki.dae@samsung.com>
parent d31bbacf

drivers/gpu/drm/exynos/exynos7_drm_decon.c

+1 −1
Original line number Diff line number Diff line
@@ -137,7 +137,7 @@ static void decon_ctx_remove(struct decon_context *ctx) 
static u32 decon_calc_clkdiv(struct decon_context *ctx,

		const struct drm_display_mode *mode)

{

	unsigned long ideal_clk = mode->clock;

	unsigned long ideal_clk = mode->clock * 1000;

	u32 clkdiv;



	/* Find the clock divider value that gets us closest to ideal_clk */