Commit f43e6ddb authored by Biju Das's avatar Biju Das Committed by Wim Van Sebroeck
Browse files

watchdog: rzg2l_wdt: Use force reset for WDT reset



This patch uses the force reset(WDTRSTB) for triggering WDT reset for
restart callback. This method(ie, Generate Reset (WDTRSTB) Signal on
parity error)is faster compared to the overflow method for triggering
watchdog reset.

Overflow method:
	reboot: Restarting system
	Reboot failed -- System halted
	NOTICE:  BL2: v2.5(release):v2.5/rzg2l-1.00-27-gf48f1440c

Parity error method:
	reboot: Restarting system
	NOTICE:  BL2: v2.5(release):v2.5/rzg2l-1.00-27-gf48f1440c

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: default avatarGuenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/20220225175320.11041-7-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarGuenter Roeck <linux@roeck-us.net>
Signed-off-by: default avatarWim Van Sebroeck <wim@linux-watchdog.org>
parent baf1aace
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+7 −7
Original line number Diff line number Diff line
@@ -21,8 +21,11 @@
#define WDTSET		0x04
#define WDTTIM		0x08
#define WDTINT		0x0C
#define PECR		0x10
#define PEEN		0x14
#define WDTCNT_WDTEN	BIT(0)
#define WDTINT_INTDISP	BIT(0)
#define PEEN_FORCE	BIT(0)

#define WDT_DEFAULT_TIMEOUT		60U

@@ -117,17 +120,14 @@ static int rzg2l_wdt_restart(struct watchdog_device *wdev,
{
	struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);

	/* Reset the module before we modify any register */
	reset_control_reset(priv->rstc);

	clk_prepare_enable(priv->pclk);
	clk_prepare_enable(priv->osc_clk);

	/* smallest counter value to reboot soon */
	rzg2l_wdt_write(priv, WDTSET_COUNTER_VAL(1), WDTSET);
	/* Generate Reset (WDTRSTB) Signal on parity error */
	rzg2l_wdt_write(priv, 0, PECR);

	/* Enable watchdog timer*/
	rzg2l_wdt_write(priv, WDTCNT_WDTEN, WDTCNT);
	/* Force parity error */
	rzg2l_wdt_write(priv, PEEN_FORCE, PEEN);

	return 0;
}