Commit f50e5ddc authored by Clément Léger's avatar Clément Léger Committed by Geert Uytterhoeven
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ARM: dts: renesas: r9a06g032: Describe GMAC1 



The r9a06g032 SoC of the RZ/N1 family features two GMAC devices named
GMAC1/2, that are based on Synopsys cores.  GMAC1 is connected to a
RGMII/RMII converter that is already described in this device tree.

Signed-off-by: default avatarClément Léger <clement.leger@bootlin.com>
[rgantois: commit log]
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarRomain Gantois <romain.gantois@bootlin.com>
Link: https://lore.kernel.org/r/20240513-rzn1-gmac1-v7-7-6acf58b5440d@bootlin.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent b4944dc7

arch/arm/boot/dts/renesas/r9a06g032.dtsi

+18 −0
Original line number Diff line number Diff line
@@ -316,6 +316,24 @@ dma1: dma-controller@40105000 { 
			data-width = <8>;

		};



		gmac1: ethernet@44000000 {

			compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac";

			reg = <0x44000000 0x2000>;

			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";

			clocks = <&sysctrl R9A06G032_HCLK_GMAC0>;

			clock-names = "stmmaceth";

			power-domains = <&sysctrl>;

			snps,multicast-filter-bins = <256>;

			snps,perfect-filter-entries = <128>;

			tx-fifo-depth = <2048>;

			rx-fifo-depth = <4096>;

			pcs-handle = <&mii_conv1>;

			status = "disabled";

		};



		gmac2: ethernet@44002000 {

			compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac";

			reg = <0x44002000 0x2000>;